DAC1405D650HW/C1,5 NXP Semiconductors, DAC1405D650HW/C1,5 Datasheet - Page 17
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DAC1405D650HW/C1,5
Manufacturer Part Number
DAC1405D650HW/C1,5
Description
IC DAC 14BIT 650MSPD DL 100HTQFP
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1405D650HWC15.pdf
(45 pages)
Specifications of DAC1405D650HW/C1,5
Settling Time
20ns
Number Of Bits
14
Data Interface
SPI™
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
1.4W
Operating Temperature
-45°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286775518
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DAC1405D650HW/C1,5
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NXP Semiconductors
DAC1405D650
Product data sheet
10.2.4 Registers detailed description
Please refer to
tables, all the values emphasized in bold are the default values.
Table 10.
Default settings are shown highlighted.
Table 11.
Default settings are shown highlighted.
Bit
7
6
5
3
2
1
0
Bit
7
6
5
Symbol
NCO_ON
NCO_LP_SEL
INV_SIN_SEL
3W_SPI
SPI_RST
CLK_SEL
MODE_SEL
CODING
IC_PD
GAP_PD
Symbol
COMMon register (address 00h) bit description
TXCFG register (address 01h) bit description
Table 9
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 September 2010
for a register overview and their default values. In the following
Dual 14-bit DAC, up to 650 Msps; 2×, 4× and 8× interpolating
Access Value Description
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x / (sin x) function
NCO
low-power NCO
disabled (the NCO phase is reset to 0)
enabled
disabled
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h respectively
disabled
enabled
serial interface bus type
serial interface reset
data input latch
input data mode
coding
power-down
internal bandgap power-down
4 wire SPI
3 wire SPI
no reset
performs a reset on all registers except 0x00
at CLK rising edge
at CLK falling edge
dual port
interleaved
binary
two’s compliment
disabled
all circuits (digital and analog, except SPI)
are switched off
power-down disabled
internal bandgap references are switched off
DAC1405D650
© NXP B.V. 2010. All rights reserved.
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