MT9JSF25672AZ-1G4D1 Micron Technology Inc, MT9JSF25672AZ-1G4D1 Datasheet - Page 5

• Manufacturer Part Number: MT9JSF25672AZ-1G4D1
• Description: MODULE DDR3 SDRAM 2GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT9JSF25672AZ-1G4D1

• Main Category: DRAM Module
• Module Type: 240UDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Number Of Elements: 9
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Memory Type: DDR3 SDRAM
• Memory Size: 2GB
• Speed: 1333MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 7: Pin Descriptions
PDF: 09005aef8360c8e6
jsf9c128_256_512x72az.pdf - Rev. C 9/09 EN
RAS#, CAS#, WE#
CK0, CK0#
DQS#[8:0]
DQ[63:0]
DQS[8:0]
Symbol
DM[8:0]
A[15:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
ODT0
CKE0
SDA
S0#
SCL
(LVCMOS)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as "BL on-the-fly" dur-
ing CAS commands. The address inputs also provide the op-code during the mode
register command set. A[13:0] address 1Gb DDR3 devices; A[14:0] address 2Gb devices,
and [15:0] address 4Gb devices.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address in-
put signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH, along with the input data, during a write access. DM is sam-
pled on both edges of the DQS. Although the DM pins are input-only, the DM loading is
designed to match that of the DQ and DQS pins.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will
be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW CMOS input referenced to V
er is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
≤ 0.2 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize com-
munication to and from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
1GB, 2GB, 4GB (x72, ECC, SR) 240-Pin DDR3 SDRAM UDIMM
DD
.
5
2
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
©2008 Micron Technology, Inc. All rights reserved.
. The RESET# input receiv-
2
C bus.
DD
and DC LOW