FWIXP420ABD Intel, FWIXP420ABD Datasheet - Page 89
FWIXP420ABD
Manufacturer Part Number
FWIXP420ABD
Description
Manufacturer
Intel
Datasheet
1.FWIXP420ABD.pdf
(128 pages)
Specifications of FWIXP420ABD
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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Datasheet—Intel
Figure 16.
Table 47.
June 2007
Document Number:
PCI Input Timing
PCI Bus Signal Timings
®
T
T
T
T
T
T
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Symbol
252479-007US
clk2outb
clk2out
setupb
setup
rst-off
hold
IXP42X product line and IXC1100 control plane processors
Input
See the timing measurement conditions.
Parts compliant to the 3.3 V signaling environment.
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup
times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a
setup of 12 ns for 33 MHz and 5 ns for 66 MHz.
RST# is asserted and de-asserted asynchronously with respect to CLK.
All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
Setup time applies only when the device is not driving the pin. Devices cannot drive and receive
signals at the same time.
Timing was tested with a 70-pF capacitor to ground.
For additional information, see the PCI Local Bus Specification, Rev. 2.2.
CLK
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Clock to output for all point-to-
point signals. This is the
PCI_GNT_N and PCI_REQ_N(0)
only.
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Input setup time for all point-to-
point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
Input hold time from clock.
Reset active-to-output float delay
Parameter
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
10, 12
Min.
2
2
7
0
33 MHz
T
setup(b)
Max.
Inputs
11
12
40
Valid
T
Min.
hold
1
1
3
5
0
66 MHz
Max.
40
6
6
Units
ns
ns
ns
ns
ns
ns
A9573-01
1, 2, 5, 7,
1, 2, 5, 7,
4, 6, 7,
5, 6, 7,
Datasheet
4, 7,
4, 7,
Notes
8
8
8
8
8
8
89
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