FWIXP420ABD Intel, FWIXP420ABD Datasheet - Page 36
FWIXP420ABD
Manufacturer Part Number
FWIXP420ABD
Description
Manufacturer
Intel
Datasheet
1.FWIXP420ABD.pdf
(128 pages)
Specifications of FWIXP420ABD
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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Functional Signal Descriptions
Table 9.
June 2007
36
High-Speed, Serial Interface 0
HSS_TXFRAME0
HSS_TXDATA0
HSS_TXCLK0
HSS_RXFRAME0
HSS_RXDATA0
HSS_RXCLK0
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Reset
Post
VI
Z
Z
Z
Z
Z
Type
O/D
I/O
I/O
I/O
I/O
I
†
Table 5 on page
The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to allow an
external source become synchronized with the transmitted data. Often known as a Frame Sync signal.
Configured as an input upon reset.
Should be pulled high
Transmit data out. Open Drain output.
Must be pulled high with a 10-KΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output. The clock can be
a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the transmitted data. Configured as an input
upon reset. Frame sync and data can be selected to be generated on the rising or falling edge of the transmit
clock.
Should be pulled high
The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to allow an
external source to become synchronized with the received data. Often known as a Frame Sync signal.
Configured as an input upon reset.
Should be pulled high
Receive data input. Can be sampled on the rising or falling edge of the receive clock.
Should be pulled high
The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The clock can be
from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset.
Should be pulled high
30.
††
††
††
††
††
with a 10-KΩ resistor when not being utilized in the system.
with a 10-KΩ resistor when not being utilized in the system.
with a 10-KΩ resistor when not being utilized in the system.
through a 10-KΩ resistor when not being utilized in the system.
with a 10-KΩ resistor when not being utilized in the system.
Intel
®
IXP45X and Intel
CCP
.
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US
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