CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 8

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. Search Coprocessor Pin Description (continued)
Document #: 38-02043 Rev. *C
Associated SRAM Interface
Note:
3.
IFC_CFG[2:0]
SDATA[63:0]/
Configuration
SADR[23:0]
XVER_0_L
XVER_1_L
XVER_2_L
Parameter
BIG/LTL_L
CMD[8:0]
DQ[67:0]
ORST_L
XVER_0
XVER_1
XVER_2
IWIDTH
Detailed information on the external transceiver is given in ”Information on External Transceivers” on page 25.
DQ_72
SOE_L
CMDV
SCLK
FULL
ACK
EOT
SSF
SSV
Type
I/O
I/O
IO
IO
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Reset Output to the NSE. Driving ORST_L low initializes the NSE.
Command Bus to the NSE. Bits [1:0] specify the command and [8:2] contain the command param-
eters. The descriptions of individual commands explain the details of the parameters. The encoding
of commands based on the [1:0] field are: 00: Read; 01: Write; 10: Search; 11: Learn.
Command Valid to the NSE. Qualifies the CMD bus.
0: No command.
1: Command valid.
NSE Address/Data Bus. This signal carries the Read and Write address and data during register,
data, and mask array operations. It carries the compare data during search operations. It also carries
the SSRAM address during SSRAM accesses to the SSRAMs containing the associative data.
When the CYNSE70128 NSE is used, the four additional DQ bits DQ[68:71] on the
CYNSE70128 should be connected to the DQ_72 output from the CYNPC80192. The DQ_72
signal is driven low from the CYNPC80192.
Read Acknowledge. This signal indicates that valid data is available on the DQ bus during register,
data, and mask array Read operations to the NSE, or that the data is available on the SRAM data
bus during Read operations of the SRAM containing associative data.
End of Transfer. This signal indicates the end of a burst transfer during Read or Write burst opera-
tions to the NSE.
Search Successful Flag. This signal indicates that the search was successful in the NSE bank.
Search Successful Flag Valid. When asserted, this signal qualifies the SSF signal.
NSE entries full indicator.
Transceiver enable for driving signals to the NSE. Active high
Transceiver enable for driving signals from the NSE. Active low.
Transceiver enable for driving signals to the NSE. Active high.
Transceiver enable for driving signals from the NSE. Active low.
Transceiver enable for driving signals to the NSE. Active high.
Transceiver enable for driving signals from the NSE. Active low.
SRAM Data/Address. This bus contains either the data from the associative SSRAM or the ADR
(Index) from an NSE, depending on the value of the SRAM present bit in CFG register 0.
{SDATA[63:0]} from SSRAMs should be connected to the 64-bit bus if the associative SSRAM is
present, or else {SADR[23:0]} from the NSEs should be connected to the 64-bit bus.
SSRAM Output Enable. This signal is the output enable control for the off-chip SSRAM bank that
contains associative data and is driven by the NSE.
SSRAM Clock. This is the same in phase and frequency as the one created internally by the NSE.
It is generated by dividing CLK by two, and is used to drive the SSRAM CLK input.
This signal selects coprocessor data bus width. 1: 64 bits; 0: 32 bits.
This selects how data from the network processor is interpreted.
1: Big Endian; 0: Little Endian.
This signal selects coprocessor interface type:
000: NoBL pipelined mode
001: NoBL flowthrough mode
010: SyncBurst pipelined mode (early Write)
011: SyncBurst pipelined mode (late Write)
100-111: Reserved.
Description
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[3]
[3]
[3]
[3]
[3]
[3]
CYNCP80192
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