CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 7

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

4.0
Table 4-1 provides information on pins and signal names for
the CYNCP80192 device. Under the “Type” heading, I = Input,
O = Output, and T = three-state.
Table 4-1. Search Coprocessor Pin Description
Document #: 38-02043 Rev. *C
Network Processor Interface
NSE Command and DQ Bus
Note:
2.
INTR/INTR_L
DESC_AFUL
DATA[63:0]
Parameter
BW_L[7:0]
CPID[7:0]
SE_FULL
ADR[9:0]
IRST_L
BWE_L
“CLK” is an internal clock signal.
CLK2X
PHS_L
CE2_L
R/W_L
CLK
STRB
CE_L
OE_L
CE2
Signal Description
[2]
Type
IO
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Synchronous Reset Input. Active low. Initializes the device to a known state.
Coprocessor Clock Input. CLK may be run up to 100 MHz.
Coprocessor Location Address. This 10-bit address bus ADRs up to 1024 32-bit locations in the
coprocessor. These 1024 locations are further divided into 512 32-bit locations of CFG area and
512 32-bit locations of the operating register area. When the data bus is configured as 64 bits wide
(using the IWIDTH pin described below), the ADR[0] is ignored by the device. When the data bus
is configured as 32 bits wide (using the IWIDTH pin described below), all the ADR bits are used by
the device.
Coprocessor Data Bus. Only the [31:0] field of this bus is used when the coprocessor is configured
for a 32-bit interface (using the IWIDTH pin described below).
Coprocessor Chip Enable. This active low signal is used to enable the device. This is one of the
three chip enables (CEs) to the coprocessor. All three CEs must be active to select the coprocessor.
Coprocessor Chip Enable. This active low signal is used to enable the device. This is another one
of the three CEs to coprocessor. All three CEs must be active to select the coprocessor.
Coprocessor Chip Enable. This active high signal is used to enable the device. This is another
one of the three CEs to the coprocessor. All three CEs must be active to select the coprocessor.
Read/Write. This input determines whether it is a Read or a Write cycle. A low on this pin means it
is a Write operation, and a High means it is a Read operation.
Coprocessor Output Enable. This active low asynchronous signal enables the output drivers of
the data bus.
Synchronous Byte Write Enables. These active low signals allow individual bytes to be written
when a Write cycle is active. When the data bus is configured as 32 bits wide, only BW_L[3:0] is
used and the BW_L[7:4] should be tied to V
Byte Write Enable. This active low signal allows the byte Write signals (BW_L[7:0]) to control the
Write operation.
When the done bit is set in result register 0, STRB qualifies the CPID[7:0]. The network processor
can use STRB signal to latch the CPID signals.
Context ID and Processor ID. When the result is Ready in the descriptor, the NDC outputs the
processor and context IDs are concatenated as follows: {processor ID, context ID}. The bit length
of the processor and context IDs can be programmed using the CFG register 0 (see CPCFG). See
the STRB signal description also.
This interrupt pin is asserted when the SE_FULL, DESC_AFULL, or error bits filed is set in the error
status register. Interrupt can be active high or low, depending upon the polarity selected in the CFG
register.
NSE table full indicator to the network processor.
This bit indicates that the descriptor array is almost full. When this flag is set, the processor can
send only two more commands to the descriptor. The DESC_AF flag will be cleared if more that two
descriptors are available.
NSE Master Clock. CYNPC80192 drives this CLK to the NSE. The frequency of this CLK is twice
the frequency of the NSE. This CLK runs up to 100 MHz and is derived by buffering the input CLK
at the coprocessor interface.
Phase Signal to the NSE. This signal runs at half the frequency of CLK2X and synchronizes the
alignment of the instruction to the NSE.
Description
DD
externally.
CYNCP80192
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