GWIXP460BADT Intel, GWIXP460BADT Datasheet - Page 71
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GWIXP460BADT
Manufacturer Part Number
GWIXP460BADT
Description
Manufacturer
Intel
Datasheet
1.GWIXP460BADT.pdf
(163 pages)
Specifications of GWIXP460BADT
Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Package Information
Table 16.
May 2005
71
ETHB_RXDV /
SMII_RXSYNC
ETHB_COL
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† Please refer to Intel
Name
see
Table 1 on page
MII/SMII Interfaces (Sheet 4 of 8)
®
IXP45X and Intel
Power
Reset
on
Z
Z
14.
†
Reset
VI
VI
Table 10 on page
®
†
IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired
Software
Enables
Normal
Reset
After
Until
VI
VI
46.
Software
Enables
Normal
After
®
VI
VI
IXP45X and Intel
Type
I
I
†
MII Mode of Operation:
Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. This
MAC interface does not contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
In Source Synchronous mode of operation, this signal is an input from a synchronous pulse
created once every 10 SMII_RXCLK reference clocks to signal the start of the next 10 bits of data
to be received. SMII_RXCLK Reference clock operates at 125MHz.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the NPE-B
Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse (refer to Expansion Bus Controller chapter of
the Intel
and is not being used in a system design, this interface/signal is not required for any connection.
MII Mode of Operation:
Asserted by the PHY when a collision is detected by the PHY. This MAC interface does not
contain hardware hashing capabilities local to the interface.
SMII Mode of Operation:
Not used.
When this interface is disabled via the NPE-B Ethernet 0 and/or the NPE Ethernet 1-3 soft fuse
(refer to Expansion Bus Controller chapter of the Intel
of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
®
• When NPE B is configured in MII mode of operation and the signal is not being used, it
• When NPE B is configured in SMII mode of operation, this signal must be pulled high with a
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
should be pulled low through a 10-KΩ resistor.
10-KΩ resistor.
®
IXP45X and Intel
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Developer’s Manual)
®
Description
IXP46X Product Line of Network Processors Datasheet
®
IXP45X and Intel
Document Number:
®
IXP46X Product Line
306261-002
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