GWIXP460BADT Intel, GWIXP460BADT Datasheet - Page 159
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GWIXP460BADT
Manufacturer Part Number
GWIXP460BADT
Description
Manufacturer
Intel
Datasheet
1.GWIXP460BADT.pdf
(163 pages)
Specifications of GWIXP460BADT
Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Table 79.
Intel
Document Number:
®
IXP45X and Intel
NOTES:
Symbol
1. HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the
2. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source as
3. The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of the
4. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP45X/IXP46X
5. The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP45X/IXP46X
6. Timing was designed for a system load between 5 pF and 30 pF for high drive setting
T1
T2
T3
T4
T5
T6
T7
T8
T9
IXP45X/IXP46X network processors. The signals are shown to be synchronous for illustrative purposes and are
not required to be synchronous.
inputs into the IXP45X/IXP46X network processors. Always applicable to HSS_RXDATA.
given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK and
HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.
network processors to an external source. Always applicable to HSS_TXDATA.
network processors. The slowest clock speed that can be accepted or driven is 512 KHz. The maximum clock
speed that can be accepted or driven is 8.192 MHz. The clock duty cycle accepted will be 50/50 + 20%.
High-Speed, Serial Timing Values
306261-002
®
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the rising edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the rising edge of clock
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the falling edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the falling edge of clock
Rising edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Falling edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after rising edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
Output Hold Delay after falling edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
HSS_TXCLK period and HSS_RXCLK period
IXP46X Product Line of Network Processors Datasheet
Parameter
1/8.192 MHz 1/512 KHz
Min.
5
0
5
0
0
0
Electrical Specifications
Max.
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
May 2005
1, 2,
1, 2,
1, 2,
1, 2,
1,
1, 3,
1, 3,
1, 3,
5
Notes
4
3
3
3
3
4
4
4
159
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