PEF2054NV21XT Infineon Technologies, PEF2054NV21XT Datasheet - Page 100

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

are set to logical 1 (inactive).
Note that the internal operation of the EPIC is not affected in standby mode, i.e. the
received PCM data is still written into the downstream data memory and may still be
processed by the EPIC (switched to the CFI or to the P, compared with other input line,
etc.)
In operational mode (OMDR:PSB = 1), the PCM output pins transmit the contents of the
upstream data memory data field or may be set to high impedance via the data memory
tristate field (refer to chapter 5.3.3.2).
PCM Input Comparison PMOD:AIC1 … AIC0
If the PCM input comparison is enabled, the EPIC checks the contents of two PCM
receive lines (physical ports) against each other for mismatches. (Also refer to
chapter 5.8.2).
The comparison function is operational in all PCM modes, a redundant PCM line which
can be switched over to by means of the PMOD:AIS bits is of course only available in
PCM modes 1and 2.
AIC0 set to logical 1 enables the comparison function between RxD0 and RxD1.
AIC1 set to logical 1 enables the comparison function between RxD2 and RxD3.
AIC1, AIC0 set to logical 0 disables the respective comparison function.
PCM Standby Mode OMDR:PSB
In standby mode (OMDR:PSB = 0), the PCM interface output pins TxD0 … 3 are set to
high impedance and those (TSC#) pins which are actually used as tristate control signals
Semiconductor Group
100
Application Hints
PEB 2055
PEF 2055