PEB20571F-V31 Infineon Technologies, PEB20571F-V31 Datasheet - Page 152

• Manufacturer Part Number: PEB20571F-V31
• Manufacturer: Infineon Technologies

Specifications of PEB20571F-V31

• Lead Free Status / Rohs Status: Not Compliant

Figure 53
Example for a single-cycle DMA transfer mode in receive direction (data is read from
DELIC and written to memory) in Intel/Infineon Mode.
1. The DMA mailbox contains data (the receive mailbox contains up to 16 bytes of data)
2. DELIC requests DMA service via DREQR
3. DMA controller issuses a DMA Acknowledge (DACK) signal for addressing the DMA
4. In parallel, when the read data are stable on the bus, the DMA controller writes the
Note: In Intel/Infineon Mode, WR is used as "read" signal for the receive mailbox.
An example for a single-cycle DMA transfer in Intel/Infineon mode in transmit direction
(data is read from memory and written into DELIC) is shown in
Data Sheet
mailbox and a "read" signal for indicating DELIC that it will read the receive mailbox
data directly into the memory using ADDR and WR.
Single cycle DMA transfer mode for Receive Data
Controller
1-Cycle-Mode
DMA
DREQR
ADDR
135
DACK
+ WR
WR
Memory
Mailbox
DELIC
DMA
Figure
Data
Data Bus
53:
Functional Description
Figure
54:
PEB 20570
PEB 20571
2003-07-31