PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 46

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.4
Access in the multiplexed P-interface mode:
Access in the demultiplexed P-interface mode:
Reset value: 00
IR
COV
4.5
Access in the multiplexed P-interface mode:
Access in the demultiplexed P-interface mode:
An indirect access is performed by reading/writing three consecutive bytes (first byte =
control byte, second byte = data byte, third byte = address byte) to/from IAR.
Bit 7
K1, K0
C3 – C0
K1, K0
00
10/01
11
X = don’t care; – is not needed to define type of access
Semiconductor Group
IA7
C3
D7
A logical 1 disables the corresponding interrupt.
Initialization Request mask; the initialization request is masked (IR = 1)
Conference Overflow mask; the conference overflow is masked (COV = 1)
Conference Mask Register (CMR)
Indirect Access Register (IAR)
AD7
IA6
C3 – C0
X
0
4
1
4
6
8
A
0
0
C2
D6
H
H
H
H
H
H
H
H
control the indirect access according to the following table
additional programming bits
H
H
0
, 2
, 3
– F
H
H
H
H
IA5
K1
D5
IR
–
–
–
–
–
–
–
0
1
D8
IA4
Type of Access
Read CM
Write CM: transp. switch, att. value programmable with C3 … C0
Write CM: conf. switch, att. value programmable with D8 – D6
Write CCM, first access
Read CCM, first access
Write CCM, second access
Read CCM, second access
Write indirect register
Read indirect register
D4
K0
COV
IA3
C1
D3
0
46
IA2
C0
D2
0
IA1
D9
D1
Write, address: 4
Write, address: 2
Read/write, address: 2
Read/write, address: 1
Detailed Register Description
0
IA0
D8
D0
Bit 0
0
Control Byte
Data Byte
Address Byte
AD0
H
H
0
PEB 2445
H
H
02.96