PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 138

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

W:MADR
W:MAAR
W:MACR
The idle code can, of course, only be transmitted on the TxD# line if the corresponding
tristate bits are enabled (refer to chapter 5.3.3.2):
W:MADR
W:MAAR
W:MACR
For test purposes the idle code can also be read back:
W:MAAR
W:MACR
wait for STAR:MAC = 0
R:MADR
In PCM mode 2 the idle pattern “0110” shall be transmitted in bit positions 3 … 0 of time
slot 63, bits 7 … 4 shall be tristated:
W:MADR
W:MAAR
W:MACR
Programming of the desired tristate functions:
W:MADR
W:MAAR
W:MACR
Examples
In PCM mode 0 the idle code “1010 0101
Semiconductor Group
= 1010 0101
= 1100 0000
= 0000 1000
= XXXX 1111
= 1100 0000
= 0110 0000
= 1100 0000
= 10XX X000
= 1010 0101
= XXXX 0110
= 1011 1111
= 0001 0000
= XXXX 0011
= 1011 1111
= 0110 0000
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
; idle code
; address of upstream PCM time slot 16 of port 0
: write access, MOC code “0001”
; all 8 bits of addressed time slot to low impedance
; address of upstream PCM time slot 16 of port 0
: write access, MOC code “1100”
; address of upstream PCM time slot 16 of port 0
: read access, MOC code “0XXX”
; idle code
; idle code
; address of upstream PCM time slot 63
; write access, MOC code “0010”
; bits 7 … 4 to high impedance, bits 3 … 0 to low
; address of upstream PCM time slot 63
; write access, MOC code “1100”
according to figure 48
according to figure 48
according to figure 48
according to figure 48
impedance
according to figure 48
B
138
” shall be transmitted in time slot 16 of port 0:
Application Hints
PEB 2055
PEF 2055