AD8341-EVAL Analog Devices Inc, AD8341-EVAL Datasheet - Page 14

• Manufacturer Part Number: AD8341-EVAL
• Manufacturer: Analog Devices Inc

Specifications of AD8341-EVAL

• Lead Free Status / Rohs Status: Not Compliant

AD8341
The 3 dB bandwidth is set by choosing C
following equation:
This equation has been verified for values of C
0.1 µF (bandwidth settings of approximately 4.5 kHz to 43 MHz).
INTERFACING TO HIGH SPEED DACs
The AD977x family of dual DACs is well suited to driving the I
and Q vector controls of the AD8341. While these inputs can in
general be driven by any DAC, the differential outputs and bias
level of the ADI TxDAC® family allows for a direct connection
between DAC and modulator.
The AD977x family of dual DACs has differential current out-
puts. The full-scale current is user programmable and is usually
set to 20 mA, that is, each output swings from 0 mA to 20 mA.
The basic interface between the AD9777 DAC outputs and the
AD8341 I and Q inputs is shown in Figure 33. The Resistors R1
and R2 set the dc bias level according to the equation:
For example, if the full-scale current from each output is 20 mA,
each output will have an average current of 10 mA. Therefore to
set the bias level to the recommended 0.5 V, R1 and R2 should
be set to 50 Ω each. R1 and R2 should always be equal.
If R3 is omitted, this will result in an available swing from
the DAC of 2 V p-p differential, which is twice the maximum
voltage range required by the AD8341. DAC resolution can be
maximized by adding R3, which scales down this voltage
according to the following equation:
AD9777
Bias Level = Average Output Current × R1
Full
f
2
3dB
I
I
I
I
OUTA1
OUTB1
OUTA2
OUTB2
×
Scale
I
≈
MAX
45
C
Figure 33. Basic AD9777 to AD8341 Interface
FLT
(
kHz
Swing
R1
R1
R2
R1
R2
+
||
×
0.5
(
10
R2
=
pF
nF
+
R3
LOW-PASS
LOW-PASS
OPTIONAL
OPTIONAL
)
FILTER
FILTER
)
×
⎡
⎢ ⎣
1
−
R2
R2
+
FLT
R3
according to the
FLT
R3
R3
⎤
⎥ ⎦
from 10 pF to
IBBM
QBBM
IBBP
QBBP
AD8341
Rev. 0 | Page 14 of 20
Figure 34 shows the relationship between the value of R3 and
the peak baseband voltage with R1 and R2 equal to 50 Ω.
From Figure 34, it can be seen that a value of 100 Ω for R3 will
provide a peak-to-peak swing of 1 V p-p differential into the
AD8341’s I and Q inputs.
When using a DAC, low-pass image reject filters are typically
used to eliminate the Nyquist images produced by the DAC.
They also provide the added benefit of eliminating broadband
noise that might feed into the modulator from the DAC.
CDMA2000 APPLICATION
To test the compliance to the CDMA2000 base station standard,
a single-carrier CDMA2000 test model signal (forward pilot,
sync, paging, and six traffic as per 3GPP2 C.S0010-B, Table
6.5.2.1) was applied to the AD8341 at 1960 MHz. A cavity tuned
filter was used to reduce noise from the signal source being
applied to the device. The 6.8 MHz pass band of this filter is
apparent in the subsequent spectral plots.
Figure 35 shows a plot of the spectrum of the output signal
under nominal conditions. P
V
Noise and distortion is measured in a 1 MHz bandwidth at
±2.25 MHz carrier offset (30 kHz measurement bandwidth).
BBQ
1.15
1.13
1.10
1.08
1.05
1.02
1.00
0.97
0.95
0.92
0.90
0.88
0.85
0.82
0.80
0.77
0.75
0.72
0.70
= 0.353 V, i.e., V
50 55 60 65 70 75 80 85 90
Figure 34. Peak-to-Peak DAC Output Swing vs.
Swing Scaling Resistor R3 (R1 = R2 = 50 Ω)
IBBP
− V
IBBM
OUT
(Ω)
is equal to −4 dBm and V
= V
95
QBBP
100 105
− V
110
QBBM
115 120
= 0.353 V.
125
130
BBI
=