AD8341-EVAL Analog Devices Inc, AD8341-EVAL Datasheet
AD8341-EVAL
Specifications of AD8341-EVAL
AD8341-EVAL Summary of contents
Page 1
... The DSOP pin allows the output stage to be disabled quickly in order to protect subsequent stages from overdrive. The AD8341 operates off supply voltages from 4. 5.25 V while consuming approximately 125 mA. The AD8341 is fabricated on Analog Devices’ proprietary, high performance 25 GHz SOI complementary bipolar IC process ...
Page 2
... Noise and Distortion.................................................................. 11 Gain and Phase Accuracy.......................................................... 11 RF Frequency Range .................................................................. 11 REVISION HISTORY 7/04—Revision 0: Initial Version Applications..................................................................................... 12 Using the AD8341 ...................................................................... 12 RF Input and Matching ............................................................. 12 RF Output and Matching .......................................................... 13 Driving the I-Q Baseband Controls......................................... 13 Interfacing to High Speed DACs.............................................. 14 CDMA2000 Application............................................................ 14 WCDMA Application ................................................................ 15 Evaluation Board ...
Page 3
... RFOP, RFOM (Pins 9 and 10) Includes load current DSOP (Pin 13) (See Figure 24) DSOP = 5 V Delay following high-to-low transition until RF output amplitude is within 10% of final value. Delay following low-to-high transition until device produces full attenuation Rev Page AD8341 Min Typ Max Unit 1.5 2.4 GHz −4.5 dB − ...
Page 4
... AD8341 ABSOLUTE MAXIMUM RATINGS Table 2. Parameters Supply Voltage VPRF, VPS2 DSOP IBBP, IBBM, QBBP, QBBM RFOP, RFOM RF Input Power at Maximum Gain (RFIP or RFIM, Single-Ended Drive) Equivalent Voltage Internal Power Dissipation θ (With Pad Soldered to Board) JA Maximum Junction Temperature Operating Temperature Range ...
Page 5
... Output disable. Pull high to disable output stage. I Channel Differential Baseband Inputs. I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass corner frequency. Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal. Rev Page IFLP IFLM IBBP IBBM VPS2 DSOP AD8341 ...
Page 6
... AD8341 TYPICAL PERFORMANCE CHARACTERISTICS 0 PHASE SETPOINT = 0° –5 PHASE SETPOINT = 270° –10 –15 PHASE SETPOINT = 180° –20 PHASE SETPOINT = 90° –25 –30 –35 –40 0.1 0 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT Figure 3. Gain Magnitude vs. Gain Setpoint at Different Phase Setpoints, RF Frequency = 1900 MHz 6 PHASE SETPOINT = 315° ...
Page 7
... Not Accounted for in Plot) 12 –40°C 10 +25° +85° 1500 1600 1700 1800 1900 2000 2100 FREQUENCY (MHz) Figure 14. Output 1 dB Compression Point vs. Frequency and Temperature, Maximum Gain, Phase Setpoint = 0° AD8341 2200 2300 2400 800 900 1000 2200 2300 2400 ...
Page 8
... AD8341 25 –40° +85° 1500 1600 1700 1800 1900 2000 FREQUENCY (MHz) Figure 15. Output IP3 vs. Frequency and Temperature, Maximum Gain, Phase Setpoint = 0°, 2.5 MHz Carrier Spacing –10 1V p-p BB INPUT –15 500mV p-p BB INPUT –20 –25 250mV p-p BB INPUT –30 –35 ...
Page 9
... DSOP VOLTAGE (V) Figure 24. Output Disable Attenuation, RF Frequency = 1900 MHz, RF Input = −5 dBm 2V/DIV DSOP RF OUTPUT 100mV/DIV 2.0V Ω CH4 100mV Ω M10.0ns 5.0GS/s A CH3 TIME (10ns/DIV) Figure 25. Output Disable Response Time, RF Frequency = 1900 MHz, RF Input = 0 dBm AD8341 4.5 5.0 1.84V ...
Page 10
... The phase angle between the resultant gain vector and the positive x-axis is de- fined as the phase shift. Note that there is a nominal, systematic insertion phase through the AD8341 to which the phase shift is added. In the following discussions, the systematic insertion phase is normalized to 0°. ...
Page 11
... GAIN AND PHASE ACCURACY There are numerous ways to express the accuracy of the AD8341. Ideally, the gain and phase should precisely follow the setpoints. Figure 4 illustrates the gain error in dB from a best fit line, normalized to the gain measured at the gain setpoint = 1.0, for the different phase setpoints ...
Page 12
... RF INPUT AND MATCHING The input impedance of the AD8341 is defined by the charac- teristics of the polyphase network. The capacitive component of the network causes its impedance to roll-off with frequency albeit at a rate slower than 6 dB/octave. By using matching inductors on the order of 1 series with each of the RF inputs, RFIP and RFIM Ω ...
Page 13
... If the disable function is not needed, the DSOP pin should be tied to ground. DRIVING THE I-Q BASEBAND CONTROLS The I and Q inputs to the AD8341 set the gain and phase be- tween input and output. These inputs are differential and should normally have a common-mode level of 0.5 V. However, when differentially driven, the common mode can vary from 250 mV to 750 mV while still allowing full gain control ...
Page 14
... The full-scale current is user programmable and is usually set to 20 mA, that is, each output swings from mA. The basic interface between the AD9777 DAC outputs and the AD8341 I and Q inputs is shown in Figure 33. The Resistors R1 and R2 set the dc bias level according to the equation: Bias Level = Average Output Current × R1 For example, if the full-scale current from each output is 20 mA, each output will have an average current ...
Page 15
... Figure 37 shows that for a fixed input power, the ACP (measured in dBm) tracks the output power as the gain is changed. WCDMA APPLICATION Figure 38 shows a plot of the output spectrum of the AD8341 transmitting a single-carrier WCDMA signal (Test Model 1-64 at 2140 MHz). The carrier power is approximately −9 dBm. The differential I and Q control voltages are both equal to 0.353 V, that is, the vector is sitting on the unit circle at 45° ...
Page 16
... OUTPUT POWER dBm ACPR 5MHz OFFSET ACPR 10MHz OFFSET NOISE –50MHz OFFSET 0 0.1 0.2 0.3 0.4 IQ CONTROL VOLTAGE Figure 40. AD8341 Output Power, ACPR and Noise vs. V Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz) –40 –45 –50 –55 –60 –65 –70 –75 – ...
Page 17
... C17 and C18 are dc blocks. L1 and L2 provide dc bias for the output. L3, L4, C5, C6 Input Interface. The input impedance of the AD8341 requires 1.2 nH inductors in series with RFIP and RFIM for optimum return loss when driven by a single-ended 50 Ω line. C5 and C6 are dc blocks. ...
Page 18
... C3, C8, C10, R2, R4, R5, R6 R8, SW1 Output Disable Interface. The output stage of the AD8341 is disabled by applying a high voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving SW1 to Position A. The output disable function can also be exercised by applying an exter- nal high or low voltage to the DSOP SMA connector with SW1 in Position A. ...
Page 19
... Figure 42. Component Side Layout Figure 43. Component Side Silkscreen Rev Page AD8341 ...
Page 20
... ORDERING GUIDE Model Temperature Range 1, 2 AD8341ACPZ-WP −40°C to +85°C AD8341ACPZ-REEL7 2 −40°C to +85°C AD8341-EVAL Waffle pack Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. 4.00 BSC SQ ...