AD9410/PCB Analog Devices Inc, AD9410/PCB Datasheet - Page 14

• Manufacturer Part Number: AD9410/PCB
• Manufacturer: Analog Devices Inc

Specifications of AD9410/PCB

• Lead Free Status / Rohs Status: Not Compliant

AD9410
Timing
The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 1). In parallel mode, the
A Port has one additional cycle of latency added on-chip to line
up transitions at the data ports—resulting in a latency of seven
cycles for the A Port. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port—
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulsewidth is a maximum of 5 ns.
EVALUATION BOARD
The AD9410 evaluation board offers an easy way to test the
AD9410. The board requires an analog input, clock, and 3 V,
5 V power supplies. The digital outputs and output clocks are
available at a standard 80-lead header P2, P3. The board has
several different modes of operation, and is shipped in the fol-
lowing configuration:
•
•
•
Power Connector
Power is supplied to the board via detachable 4-pin power strips
P1, P4, P5.
VDAC – Optional DAC Supply Input (3.3 V)
EXT REF – Optional External VREF Input (2.5 V)
V
3.3 VA – Analog Supply (3.3 V)
5 V – Analog Supply (5 V)
Analog Inputs
The evaluation board accepts a 1.5 V p-p analog input signal
centered at ground at SMB J8. This input is terminated to 50 Ω
on the board at the transformer secondary, but can be termi-
nated at the SMB if an alternative termination is desired. The
input is ac-coupled prior to the transformer. The transformer is
band limited to frequencies between approximately 1 MHz and
400 MHz.
Encode
The encode input to the board is at SMB connector J1. The
input is terminated on the board with 50 Ω to ground. The
(>0.5 V p-p) input is ac-coupled and drives a high-speed
differential line receiver (MC10EL16). This receiver provides
sub- nanosecond rise times at its outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and are ac-coupled to meet the common-
mode dc levels at the AD9410 encode inputs.
DD
Output Timing = Parallel Mode
Output Format = Offset Binary
Internal Voltage Reference
– Logic Supply (3.3 V)
Data Sync (DS)
The Data Sync input, DS, can be used in applications requir-
ing that a given sample will appear at a specific output Port A or
B. When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by the
assertion (falling edge) of DS, within the timing constraints
T
synchronization T
required setup time (T
the analog value at that point in time will be digitized and avail-
able at Port B six cycles later (interleaved mode). The very next
sample, N+1, will be sampled by the next rising encode edge and
available at Port A six cycles after that encode edge (interleaved
mode). In dual parallel mode the A Port has a seven cycle latency,
the B Port has a six cycle latency, but data is available at the
same time.
REFERENCE
The AD9410 has an on-chip reference of 2.5 V available at
REF
to the REF
jumper at E1, E6. An external reference can be used placing a
jumper at E1, E3.
Output Timing
The chip has two timing modes (see timing diagram). Inter-
leaved mode is selected by Jumper E11, E7. Parallel mode is
selected by Jumper E11, E14.
Data Format Select
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 79) low at E12, E10 sets the output
format to be offset binary; setting DFS high at E12, E16 sets the
output to be two’s complement.
DS Pin
The DS, DS inputs are available at SMB connectors J9X and
J10X. The board is shipped with DS pulled to ground by R26.
DS is floating (R25X is not placed).
DAC Outputs
Each channel is reconstructed by an on-board dual channel
DAC, an AD9751 to assist in debug. The performance of the
DAC has not been optimized and will not give an accurate
measure of the full performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors. The
outputs are available at J3 and J4.
SDS
OUT
and T
(Pin 4). Most applications will simply tie this output
IN
HDS
input (Pin 5). This is accomplished by placing a
relative to an encode rising edge. (On initial
HDS
SDS
is not relevant.) If DS falls within the
) before a given encode rising edge N,