AD9410/PCB Analog Devices Inc, AD9410/PCB Datasheet - Page 13

• Manufacturer Part Number: AD9410/PCB
• Manufacturer: Analog Devices Inc

Specifications of AD9410/PCB

• Lead Free Status / Rohs Status: Not Compliant

APPLICATION NOTES
THEORY OF OPERATION
The AD9410 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantiza-
tion by the flash 10-bit core. For ease of use the part includes
an onboard reference and input logic that accepts TTL, CMOS,
or PECL levels.
USING THE AD9410
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/Hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9410, and the
user is advised to give commensurate thought to the clock source.
To limit SNR degradation to less than 1 dB, a clock source with
less than 1.25 ps rms jitter is required for sampling at Nyquist.
(Valpey Fisher VF561 is an example.) Note that required jitter
accuracy is a function of input frequency and amplitude. Consult
Analog Devices’ application note AN-501, “Aperture Uncer-
tainty and ADC System Performance,” for more information.
The ENCODE input is fully TTL/CMOS-compatible. The
clock input can be driven differentially or with a single-ended
signal. Best performance will be obtained when driving the clock
differentially. Both ENCODE inputs are self-biased to 1/3 × V
by a high impedance resistor divider. (See Equivalent Circuits
section.) Single-ended clocking, which may be appropriate for
lower frequency or nondemanding applications, is accomplished
by driving the ENCODE input directly and placing a 0.1 µF
capacitor at ENCODE.
An example where the clock is obtained from a PECL driver is
shown in Figure 11. Note that the PECL driver is ac-coupled to
the ENCODE inputs to minimize input current loading. The
AD9410 can be dc-coupled to PECL logic levels resulting in the
ENCODE input currents increasing to approximately 8 mA
typically. This is due to the difference in dc bias between the
ENCODE inputs and a PECL driver. (See Equivalent Cir-
cuits section.)
GATE
PECL
TTL/CMOS
510
GATE
GND
0.1 F
510
0.1 F
0.1 F
ENCODE
ENCODE
ENCODE
ENCODE
AD9410
AD9410
CC
Analog Input
The analog input to the AD9410 is a differential buffer. For
best dynamic performance, impedances at A
match. The analog input has been optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance will degrade
significantly if the analog input is driven with a single-ended
signal. A wideband transformer such as Minicircuits ADT1-1WT
can be used to provide the differential analog inputs for applica-
tions that require a single-ended-to-differential conversion. Both
analog inputs are self-biased by an on-chip resistor divider to a
nominal 3 V. (See Equivalent Circuits section.)
Special care was taken in the design of the Analog Input section
of the AD9410 to prevent damage and corruption of data when the
input is overdriven. The nominal input range is 1.5 V diff p-p.
The nominal differential input range is 768 mV p-p × 2.
Digital Outputs
The digital outputs are TTL/CMOS-compatible for lower power
consumption. The outputs are biased from a separate supply
(V
CMOS devices which will swing from ground to V
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total C
(20 Ω) series damping resistors on the data lines to reduce switch-
ing transient effects on performance.
Clock Outputs (DCO, DCO)
The input ENCODE is divided by two and available off-chip at
DCO and DCO. These clocks can facilitate latching off-chip,
providing a low skew clocking solution (see timing diagram).
These clocks can also be used in multiple AD9410 systems to
synchronize the ADCs. Depending on application, DCO or
DCO can be buffered and used to drive the DS inputs on a
second AD9410, ensuring synchronization. The on-chip clock
buffers should not drive more than 5 pF–7 pF of capacitance to
limit switching transient effects on performance.
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREF OUT). The input range can be adjusted by
varying the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The full-
scale range of the ADC tracks reference voltage changes linearly
within the ± 5% tolerance.
DD
), allowing easy interface to external logic. The outputs are
LOAD
3.384
3.000
2.616
< 5 pF). It is also recommended to place low value
A
A
IN
IN
IN
and AIN should
AD9410
DD
(with no