IS42S16160A7TL ISSI, Integrated Silicon Solution Inc, IS42S16160A7TL Datasheet

no-image

IS42S16160A7TL

Manufacturer Part Number
IS42S16160A7TL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S16160A7TL

Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
IS42S83200A
IS42S16160A
256 Mb Synchronous DRAM
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
FEATURES
DESCRIPTION
IS42S83200A is a synchronous 256Mb SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A is organized as 4-bank x 4,194,304-word x
16-bit. All inputs and outputs are referenced to the rising
edge of CLK.
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package: 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
- Lead-free available
tCLK
tRAS Active to Precharge Command Period (Min.)
tRCD
tAC
tRC
Icc1
Icc6
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
-6:166MHz<3-3-3>
Operation Current (Single Bank)
Self Refresh Current
Clock Cycle Time
Row to Column Delay
Access Time from CLK
Ref /Active Command Period
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
ITEM
(Max.) -6,-7,-75
(Max.)
(Max.)
(Min.)
(Min.)
(Min.)
IS42S83200A
IS42S16160A
CL=2
CL=3
CL=2
CL=3
suitable for main memories or graphic
IS42S83200A and IS42S16160A achieve very
high speed clock rates up to 166MHz, and are
memories in computer systems.
IS42S83200A/16160A
130
-6
60
42
15
-
-
5
-
3
6
130
5.4
-7
45
20
63
-
-
-
3
7
67.5
-75
110
7.5
5.4
10
45
20
-
3
6
Unit
ns
ns
ns
ns
ns
ns
mA
mA
mA
ns
ISSI
November 2005
®
1

Related parts for IS42S16160A7TL

IS42S16160A7TL Summary of contents

Page 1

... IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) 256 Mb Synchronous DRAM DESCRIPTION IS42S83200A is a synchronous 256Mb SDRAM and is organized as 4-bank x 8,388,608-word x 8-bit; and IS42S16160A is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. FEATURES ...

Page 2

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) PIN CONFIGURATION (TOP VIEW) Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 ...

Page 3

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) BLOCK DIAGRAM Memory Array 8192x1024x8 Cell Array Bank #0 Mode Register Address Buffer A0-12 BA0,1 Note:This figure shows the IS42S83200A The IS42S16160A configuration is ...

Page 4

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) PIN FUNCTION CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0-12 Input BA0,1 Input DQ0-7(x8), Input / Output DQ0-15(x16) DQM(x8), Input DQMU/L(x16) ...

Page 5

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) BASIC FUNCTIONS The IS42S83200A/16160A provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command ...

Page 6

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) COMMAND TRUTH TABLE COMMAND MNEMONIC Deselect DESEL No Operation NOP Row Address Entry & ACT Bank Activate Single Bank Precharge PRE Precharge All Banks ...

Page 7

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) FUNCTION TRUTH TABLE Current State /CS /RAS /CAS IDLE ...

Page 8

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS WRITE ...

Page 9

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS PRE - CHARGING ...

Page 10

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS RE FRESHING ...

Page 11

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) FUNCTION TRUTH TABLE (continued) CKE CKE Current State n SELF- REFRESH ...

Page 12

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) SIMPLIFIED STATE DIAGRAM MODE REGISTER SET CLK SUSPEND CKEL WRITE WRITE SUSPEND CKEH WRITEA CKEL WRITEA WRITEA SUSPEND CKEH POWER APPLIED POWER ON 12 ...

Page 13

... Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. BA0 BA1 A12 A11 A10 ...

Page 14

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) CLK Command Read Address Y DQ /CAS Latency CL= 3 BL= 4 Initial Address ...

Page 15

... IS42S16160A (4-bank x 4,194,304 - word x 16-bit) OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank ad- dresses (BA0,1). A row is indicated by the row ad- dresses A0-12. The minimum activation interval be- tween one bank and the other bank is tRRD.Multiple banks can be active state concurrently by issuing mul­ ...

Page 16

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Multi Bank Interleaving Read (CL=2, BL=4) CLK Command ACT tRCD A0-9,11-12 Xa A10 Xa BA0 Read with Auto-Precharge (CL=2, BL=4) CLK Command ...

Page 17

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) WRITE A WRITE command can be issued to any active bank. The start address is specified by A0-9(x8), A0-8(x16). 1st input data is set ...

Page 18

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is ...

Page 19

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is ...

Page 20

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [Read Interrupted by Burst Terminate] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. ...

Page 21

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE ...

Page 22

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the ...

Page 23

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [Write with Auto-Precharge Interrupted by Write or Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another ...

Page 24

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) [Read with Auto-Precharge Interrupted by Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ...

Page 25

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated ...

Page 26

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, ...

Page 27

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK ...

Page 28

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM(U,L) ...

Page 29

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply Voltage Vdd Supply Voltage for Output VddQ Input Voltage VI VO Output Voltage IO Output Current Pd Power ...

Page 30

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) AVERAGE SUPPLY CURRENT from Vdd (Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted) ITEM Operating current Precharge Standby current in Non-Power down mode Precharge Standby ...

Page 31

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) AC TIMING REQUIREMENTS (Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted) Input Pulse Levels:0.8V-2.0V Input Timing Measurement Level:1.4V Parameter Symbol tCLK CLK cycle time tCH ...

Page 32

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) SWITCHING CHARACTERISTICS (Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted) Symbol Parameter tAC Access time from CLK Output Hold time tOH from CLK Delay time ...

Page 33

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Burst Write (Single Bank) [BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 X ...

Page 34

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Burst Write (Multi Bank) [BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 X ...

Page 35

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Burst Read (Single Bank) [CL=2, BL= CLK /CS tRAS /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X ...

Page 36

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Burst Read (Multi Bank) [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 ...

Page 37

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Write Interrupted by Write [BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 ...

Page 38

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Read Interrupted by Read [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 ...

Page 39

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Write Interrupted by Read, Read Interrupted by Write [CL=2, BL= CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9,11 ...

Page 40

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Write / Read Terminated by Precharge [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X ...

Page 41

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Write / Read Terminated by Burst Terminate [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9, ...

Page 42

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Single Write Burst Read [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 X ...

Page 43

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Power-Up Sequence and Intialize CLK 200 s /CS tRP /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ NOP Power On PRE ALL ...

Page 44

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Auto Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ PRE ALL REFA All banks must ...

Page 45

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Self Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ PRE ALL Self Refresh Entry ...

Page 46

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) CLK Suspension [CL=2, BL= CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9, A10 X A12 X BA0,1 0 ...

Page 47

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) Power Down CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ PRE ALL Integrated Silicon Solution, Inc. ...

Page 48

IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Speed (ns) 166 MHz 6 143 MHz 7 133 MHz 7.5 Commercial Range: 0°C to +70°C, ...

Page 49

PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...

Related keywords