MT41J128M8HX-187E:D Micron Technology Inc, MT41J128M8HX-187E:D Datasheet - Page 194
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MT41J128M8HX-187E:D
Manufacturer Part Number
MT41J128M8HX-187E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J128M8HX-187ED.pdf
(208 pages)
Specifications of MT41J128M8HX-187E:D
Organization
128Mx8
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M8HX-187E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Synchronous ODT Mode
ODT Latency and Posted ODT
Timing Parameters
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R
modes are:
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled during precharge power-down by
In synchronous ODT mode, R
HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by
each clock edge (see Table 86 (page 195)). The ODT latency is tied to the WRITE latency
(WL) by ODTL on = WL - 2 and ODTL off = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency
(AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT
signal. The device’s internal ODT signal is delayed a number of clock cycles defined by
the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL off =
CWL + AL - 2.
Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off,
ODTH4, ODTH8,
point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R
Both are measured relative to ODTL on. The minimum R
is the point at which the device starts to turn off ODT resistance. Maximum R
time (
from ODTL off.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 116 (page 196)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
MR0[12]
t
AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
TT
turn-on time (
TT,nom
t
AON, and
or R
t
TT(WR)
AON [MAX]) is the point at which ODT resistance is fully on.
t
194
AOF. The minimum R
TT
is enabled. Based on the power-down definition, these
turns on ODTL on clock cycles after ODT is sampled
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
TT
turn-on time (
Synchronous ODT Mode
TT
turn-off time (
t
© 2006 Micron Technology, Inc. All rights reserved.
AON and
t
AON [MIN]) is the
t
AOF around
t
AOF [MIN])
TT
turn off
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