MT41J128M8HX-187E:D Micron Technology Inc, MT41J128M8HX-187E:D Datasheet - Page 139
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MT41J128M8HX-187E:D
Manufacturer Part Number
MT41J128M8HX-187E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J128M8HX-187ED.pdf
(208 pages)
Specifications of MT41J128M8HX-187E:D
Organization
128Mx8
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M8HX-187E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Figure 57: Mode Register 2 (MR2) Definition
CAS Write Latency (CWL)
Figure 58: CAS Write Latency
AUTO SELF REFRESH (ASR)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
Note:
WRITE n
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 57 (page 139)). The overall WRITE
latency (WL) is equal to CWL + AL (Figure 55 (page 135)).
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
T1
M15
0
0
1
1
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
t RCD (MIN)
M14
0
1
0
1
M10
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
0
1
1
Mode Register
M9
0
1
0
1
NOP
AL = 5
T2
R
Dynamic ODT
TT(WR)
Reserved
(R
RZQ/4
RZQ/2
TT(WR)
0 1
BA2
16
WL = AL + CWL = 11
disabled
)
1
15
BA1
14
0
NOP
BA0
T6
139
0 1
13
M7
A13
0
1
0 1
12
Self Refresh Temperature
A12 A11
Extended (0°C to 95°C)
M6
Normal (0°C to 85°C)
0
1
0 1
11
Enabled: Automatic
Disabled: Manual
Auto Self Refresh
R
CWL = 6
10
TT(WR)
(Optional)
A10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T11
9
A9
0 1
8
A8
SRT
Indicates A Break in
Time Scale
1Gb: x4, x8, x16 DDR3 SDRAM
7
A7 A6 A5 A4 A3
ASR
6
M5
0
0
0
0
1
1
1
1
5
CWL
NOP
T12
M4
DI
0
0
1
1
0
0
1
1
n
4
M3
Mode Register 2 (MR2)
0
1
0
1
0
1
0
1
3
6 CK (2.5ns > t CK ≥ 1.875ns)
7 CK (1.875ns > t CK ≥ 1.5ns)
0 1 0 1 0 1
8 CK (1.5ns > t CK ≥ 1.25ns)
n + 1
2
CAS Write Latency (CWL)
DI
A2 A1 A0
© 2006 Micron Technology, Inc. All rights reserved.
5 CK ( t CK ≥ 2.5ns)
1
Transitioning Data
Reserved
Reserved
Reserved
Reserved
0
n + 2
NOP
T13
DI
Address bus
Mode register 2 (MR2)
n + 3
DI
Don’t Care
NOP
T14
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