EVAL-ADN2816EB Analog Devices Inc, EVAL-ADN2816EB Datasheet - Page 21

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EVAL-ADN2816EB

Manufacturer Part Number
EVAL-ADN2816EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADN2816EB

Lead Free Status / Rohs Status
Supplier Unconfirmed
V
V
VTH = ADN2816 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2816. THE
V1b
V2b
DIFF
DIFF
V1
V2
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
= V2–V2b
1
VCC
TIA
V1b
V1
C
C
IN
IN
2
V2b
V2
Figure 21. Example of Baseline Wander
PIN
NIN
50Ω
50Ω
ADN2816
V
REF
Rev. A | Page 21 of 24
+
BUFFER
3
CDR
C
C
OUT
OUT
DATAOUTP
DATAOUTN
4
VREF
VTH
ADN2816