EVAL-ADN2816EB Analog Devices Inc, EVAL-ADN2816EB Datasheet
EVAL-ADN2816EB
Specifications of EVAL-ADN2816EB
EVAL-ADN2816EB Summary of contents
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FEATURES Serial data input: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator 2 I C® interface to access optional features Single-supply operation: 3.3 V Low power: ...
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ADN2816 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Jitter Specifications ....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings ............................................................ ...
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SPECIFICATIONS VCC = VEE = MIN MAX MIN MAX unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level ...
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ADN2816 JITTER SPECIFICATIONS VCC = MIN MAX MIN MAX unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Jitter Tolerance 1 Jitter tolerance ...
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OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time ...
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ADN2816 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All ...
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TIMING CHARACTERISTICS CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R LOAD V 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT ...
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ADN2816 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic 1 TEST1 2 VCC 3 VREF 4 NIN 5 PIN VEE REFCLKP 11 REFCLKN 12 VCC 13 VEE 14 ...
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I C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 MSB = 1 S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR) A( START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT ...
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ADN2816 1 Table 6. Internal Register Map Reg Name R/W Address D7 FREQ0 R 0x0 MSB FREQ1 R 0x1 MSB FREQ2 R 0x2 0 RATE R 0x3 COARSE_RD[8] MSB MISC R 0x4 x CTRLA W 0x8 F REF CTRLB W ...
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JITTER SPECIFICATIONS The ADN2816 CDR is designed to achieve the best bit-error- rate (BER) performance and to exceed the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement ...
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ADN2816 THEORY OF OPERATION The ADN2816 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that ...
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At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of ...
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ADN2816 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2816 acquires frequency from the data over a range of data frequencies from 10 Mb/s to 675 Mb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming ...
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The CTRLB[7] bit defaults this mode, the LOL pin operates in the normal operating mode, that is asserted only when the ADN2816 is in acquisition mode and deasserts when the ADN2816 has reacquired lock. HARMONIC ...
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ADN2816 Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a ...
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The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_F , where DIV_F REF divided-down reference referred to the 10 MHz to 20 MHz ...
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ADN2816 Additional Features Available via the I Coarse Data Rate Readback The data rate can be read back over the I approximately ±10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when ...
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APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ...
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ADN2816 Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN high frequency reference clock is ...
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VCC TIA C V1b IN V2b V1b V2 V2b V DIFF V = V2–V2b DIFF VTH = ADN2816 QUANTIZER THRESHOLD NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT ...
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ADN2816 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code F Code MID 0 5.3745e+ 5.3741e+ 5.4793e+ 5.5912e+ 5.7111e+ ...
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Code F Code MID 192 3.4397e+08 202 193 3.4394e+08 203 194 3.5067e+08 204 195 3.5783e+08 205 196 3.6551e+08 206 197 3.7370e+08 207 198 3.8247e+08 208 199 3.9177e+08 209 200 4.0179e+08 210 201 4.1322e+08 211 F Code F MID MID 4.2490e+08 ...
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... ADN2816ACPZ-500RL7 −40°C to +85°C 1 ADN2816ACPZ-RL7 −40°C to +85°C 1 EVAL-ADN2816EBZ RoHS Compliant Part. 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I © ...