AD7564AR-B Analog Devices Inc, AD7564AR-B Datasheet - Page 5

• Manufacturer Part Number: AD7564AR-B
• Description: IC DAC 12BIT QUAD 3.3V LP 28SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7564AR-B

• Rohs Status: RoHS non-compliant
• Settling Time: 500ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 50µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

REV. A
Timing Specifications
Parameter
t
t
t
t
t
t
t
t
t
NOTES
1
2
from a voltage level of 1.6 V for a V
of 3.3 V.
1
2
3
4
5
6
7
8
9
Not production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
t
8
2
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a V
LDAC, CLR
SDOUT(O)
CLKIN(I)
FSIN(I)
SDIN(I)
Limit at
V
180
80
80
50
50
10
125
100
80
DD
= +3 V to +3.6 V V
DD
t
DB15
5
of 5 V and from a voltage level 1.35 V for a V
Figure 2. Load Circuit for Digital Output Timing Specifications
1
t
4
(T
t
6
A
= T
Limit at
100
40
40
30
30
5
90
70
40
MIN
DD
to T
= +4.75 V to +5.25 V
TO OUTPUT
MAX
t
50pF
PIN
2
unless otherwise noted)
C
Figure 1. Timing Diagram
L
t
1
t
3
1.6mA
200µA
DB0
–5–
t
DD
8
I
I
DB15
OH
OL
of 3.3 V.
t
7
ns min
ns min
ns max
t
Units
ns min
ns min
ns min
ns min
ns min
ns min
9
+1.6V
Description
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN Setup Time
Data Setup Time
Data Hold Time
FSIN Hold Time
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR Pulse Width
DD
DB0
of 5 V and 0.6 V or 2.1 V for a V
AD7564
DD
) and timed
DD
3