Q68100A0989 OSRAM Opto Semiconductors Inc, Q68100A0989 Datasheet
Q68100A0989
Specifications of Q68100A0989
Related parts for Q68100A0989
Q68100A0989 Summary of contents
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... The SCD55100A (Red), SCD55101A (Yellow), SCD55102A (HER), SCD55103A (Green) and SCD55104A (HEG) are eight digit dot addressable matrix, Serial Input, Intelligent Display devices. The ten 3.68 mm (0.145") high digits are packaged in a rugged, high quality optically transparent, standard 7.62 mm (0.3") pin spacing 28 pin plastic DIP. ...
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... Dimensions in mm (inch) Intensity Code EIA Date Code Hue Code Z Y Seating Plane 2.54 (0.100) typ. ±0.25 (0.010) 1 Tol. non accum. 3.81 (0.150) 2 Ordering Code Q68100A0988 Q68100A0989 Q68100A0990 Q68100A0991 Q68100A0992 1.27 (0.050) typ. 0.3 (0.012) typ. 1 7.62 (0.300) ±0.51 (0.020) 1 IDOD5211 ...
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... V at 100% brightness level, viewing angle: X axis ± 55°, Y axis ± 65°) CC Description Luminous Intensity Peak Wavelength Dominant Wavelength Notes: 1. Dot to dot intensity matching at 100% brightness is 1.8:1. 2. Displays are binned for hue at 2.0 nm intervals. 3. Displays within a given intensity category have an intensity matching of 1.5:1 (max.). 2008-07-22 Symbol stg V CC ...
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SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A Data Write Cycle LOAD DATA SDCLK T SDCW Instruction Cycle LOAD SDCLK D0 DATA LOAD SDCLK DATA D0 Maximum Power Dissipation vs. Temperature 2008-07-22 T LDS SDCW T Period SDCLK ...
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... Hz <50 μA. CC Top View 28 1 Clock I/O IDCD5021 5 Conditions — =5.0 V, all inputs =5.0 V, “#” displayed in all 10 digits CC at 100% brightness at 25°C =5 (all inputs =5.0 V (all inputs = =0.4 V ...
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... Asynchronous input, when low will clear the Multiplex Counter, User RAM and Data Register. Control Word Register is set to 100% brightness and the Address Register is set to select Digit 0. The display is blanked. GND Power supply ground CLK I/O Outputs master clock or inputs external clock. ...
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... IC accepts decoded serial data, which is stored in the internal RAM. Asynchronously the RAM is read by the character multiplexer at a strobe rate that results in a flicker free display. Figure „Row and Column Location“ (page 9) shows the three functional areas of the IC. These include: the input serial data register and control logic, a 250 bits two port RAM, and an internal multiplexer/display driver ...
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... SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A The following explains how to format the serial data to be loaded into the display. The user supplies a string of bit mapped decoded characters. The contents of this string is shown in Figure „Loading Serial Character Data a“ (page 8). Figure „Loading Serial Charac- ter Data b“ ...
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... I B9 Character 9 shown in Table „Power Down“ (page 9), the display is set to 0% brightness and the internal multiplex clock is stopped. When in the Power Down mode data may still be written into the RAM. The dis- play is reactivated by loading a new Brightness Level Control Word into the display ...
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... MUX Clock rate. The MUX Clock frequency is divided by a 320 counter chain. This results in a typical strobe rate of 750 Hz. By pulling the Clock SEL line low, the display can be operated from an external MUX Clock. The external clock is attached to the CLK I/O connection (pin 15) ...
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... For further information refer to Appnotes 18 and 19 at www.osram-os.com An alternative to soldering and cleaning the display modules is to use sockets. Naturally, 28 pin DIP sockets 7.62 mm (0.300") wide with 2.54 mm (0.100") centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or DIP sockets when available for uniform package alignment. Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ ...
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... Upon power up display will come on at random. Thus the display should be reset at power-up. The reset will set the Address Register to Digit 0, User RAM is set to 0 (display blank) the Control Word is set to 0 (100% brightness with Lamp Test off) and the internal counters are reset ...
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... Cascading Multiple Displays Multiple displays can be cascaded using the CLKSEL and CLK I/O pins as shown below. The display designated as the Master Clock source should have its CLKSEL pin tied high and the slaves should have their CLKSEL pins tied low. All CLK I/O pins should be tied together ...
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... Note: If the display is already reset at Power Up, there is no need for Software Clear. 2008-07- different brightness is desired, load the proper brightness opcode into the Control Word Register. 4. Load the Digit Address into the display. 5. Load display row and column data for the selected digit. ...
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SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A User Definable Character Set Examples* Upper and Lower Case Alphabets HEX HEX CODE CODE ...
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SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A User Definable Character Set Examples* (continued) Scientific Notations, etc. HEX HEX CODE CODE ...
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SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A Revision History: 2008-07-22 Previous Version: 2006-02-20 Page Subjects (major changes since last revision) all Lead free device 6 Pin assignment corrected ublished by P OSRAM Opto Semiconductors GmbH Wernerwerkstrasse 2, D-93049 Regensburg www.osram-os.com © All ...