DAC8043GP Analog Devices Inc, DAC8043GP Datasheet - Page 12

• Manufacturer Part Number: DAC8043GP
• Description: IC DAC 12BIT MULTIPLY CMOS 8-DIP
• Manufacturer: Analog Devices Inc

Specifications of DAC8043GP

• Data Interface: Serial
• Rohs Status: RoHS non-compliant
• Settling Time: 250ns
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 500µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Resolution (bits): 12bit
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 500µA
• Digital Ic Case Style: DIP
• No. Of Pins: 8
• Number Of Channels: 1
• Resolution: 12b
• Conversion Rate: 366KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Current
• Integral Nonlinearity Error: ±0.5LSB
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

DAC8043
APPLICATIONS INFORMATION
APPLICATION TIPS
In most applications, linearity depends upon the potential
of the I
applications, the DAC is connected to an external op amp
with its noninverting input tied to ground (see Figure 16 and
Figure 17). The amplifier selected should have a low input bias
current and low drift over temperature. The amplifier’s input offset
voltage should be nulled to less than 200 μV (less than 10% of
1 LSB).
The noninverting input of the operational amplifier should have
a minimum resistance connection to ground; the usual bias
current compensation resistor should not be used. This resistor
can cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The V
have a low noise level with no transients greater than 17 V.
Unipolar Operation (2-Quadrant)
The circuits shown in Figure 16 and Figure 17 may be used with
an ac or dc reference voltage. The output of the circuit ranges
between 0 V and approximately −V
upon the digital input code. The relationship between the
digital input and the analog output is shown in Table 6. The
limiting parameters for the V
voltage range of the op amp or ±25 V, whichever is lowest.
Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming
SERIAL
Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
INPUT
DATA
SERIAL
V
CLK
10V
INPUT
REF
DATA
LD
V
CLK
10V
REF
OUT
LD
100Ω
and GND pins being equal to each other. In most
R
1
V
DAC8043
V
DAC8043
REF
REF
V
5V
V
DD
GND
5V
I
DD
GND
R
OUT
I
R
OUT
FB
(2-Quadrant)
FB
REF
50Ω
R
range are the maximum input
2
15pF
REF
DD
(4095/4096), depending
15pF
power supply should
2
3
OP77
2
3
+15V
–15V
OP42
+15V
–15V
7
4
7
4
6
6
V
OUT
V
OUT
Rev. E | Page 12 of 16
Gain error may be trimmed by adjusting R
The DAC register must first be loaded with all 1s. R
be adjusted until V
adjustable V
to yield the desired full-scale output.
In most applications, the DAC8043’s negligible zero-scale error
and very low gain error permit the elimination of the trimming
components (R
on circuit performance.
Table 6. Unipolar Code Table
Digital Input
MSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
1
2
Nominal full scale for Figure 16 and Figure 17 circuits is given by
Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by
FS
LSB
=
=
LSB
−
V
V
REF
REF
REF
, R



1
4096
and the external R



1
1
4095
4096
and R
OUT
Nominal Analog Output
(V
−
−
−
−
−
−



V
V
V
V
V
V
OUT
= −V
or
REF
REF
REF
REF
REF
REF



2
as Shown in Figure 16 and Figure 17)
V
may be omitted, with V
REF


















REF
2049
2048
2047
4095
4096
4096
4096
4096
4096
4096
( )
2
1
0
−
(4095/4096). In the case of an
1, 2
n


















2
=
=
) without adversely affecting
−
0
V
1
REF
2
, as shown in Figure 17.
REF
1
adjusted
may then