M27C2001-12B1 STMicroelectronics, M27C2001-12B1 Datasheet - Page 9

• Manufacturer Part Number: M27C2001-12B1
• Manufacturer: STMicroelectronics

Specifications of M27C2001-12B1

• Organization: 256Kx8
• Interface Type: Parallel
• In System Programmable: External
• Access Time (max): 120ns
• Package Type: PDIP
• Reprogramming Technique: OTP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Pin Count: 32
• Mounting: Through Hole
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Device operation
2.5
2.6
9/25
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the
'1' state. Data is introduced by selectively programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's and '0's can be present in the data word.
The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The
M27C2001 is in the programming mode when V
pulsed to V
pins. The levels required for the address and data inputs are TTL. V
6.25 ± 0.25V.
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a
guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II
consists of applying a sequence of 100µs program pulses to each byte until a correct verify
occurs (see
automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Figure 5.
CC
IL
Figure
. The data to be programmed is applied to 8 bits in parallel to the data output
Programming Flowchart
and V
5). During programming and verify operation, a MARGIN MODE circuit is
SS
for every eight devices. The bulk capacitor should be located near the
YES
NO
FAIL
= 25
++n
V CC = 6.25V, V PP = 12.75V
CHECK ALL BYTES
NO
2nd: V CC = 4.2V
P = 100 s Pulse
1st: V CC = 6V
VERIFY
n = 0
Addr
Last
YES
YES
PP
NO
input is at 12.75V, E is at V
++ Addr
AI00715C
CC
is specified to be
IL
and P is
M27C2001