M27C2001-12B1 STMicroelectronics, M27C2001-12B1 Datasheet - Page 8

• Manufacturer Part Number: M27C2001-12B1
• Manufacturer: STMicroelectronics

Specifications of M27C2001-12B1

• Organization: 256Kx8
• Interface Type: Parallel
• In System Programmable: External
• Access Time (max): 120ns
• Package Type: PDIP
• Reprogramming Technique: OTP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Pin Count: 32
• Mounting: Through Hole
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

M27C2001
2
2.1
2.2
2.3
2.4
Device operation
The operating modes of the M27C2001 are listed in the
required in the read mode. All inputs are TTL levels except for V
Electronic Signature.
Read Mode
The M27C2001 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
available at the output after a delay of t
been low and the addresses have been stable for at least t
Standby Mode
The M27C2001 has a standby mode which reduces the supply current from 30mA to 100µA.
The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are in a high impedance state, independent of
the G input.
Two Line Output Control
Because EPROM devices are usually used in larger memory arrays, this product features a
2 line control function which accommodates the use of multiple memory connection. The
two line control function allows:
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V
a)
b)
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
AVQV
) is equal to the delay from E to output (t
GLQV
from the falling edge of G, assuming that E has
CC
, has three segments that are of interest to
Table
AVQV
2. A single power supply is
-t
PP
GLQV
CC
and 12V on A9 for
.
and V
ELQV
Device operation
SS
). Data is
. This should
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