MT41J512M8THD-15E:D Micron Technology Inc, MT41J512M8THD-15E:D Datasheet - Page 5

• Manufacturer Part Number: MT41J512M8THD-15E:D
• Description: IC DDR3 SDRAM 4GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J512M8THD-15E:D

• Organization: 512Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Compliant

Table 3:
PDF: 09005aef83188bab/Source: 09005aef83169de6
MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN
RAS#, CAS#, WE#
A12/BC#, A11,
A10/AP, A[9:0]
TDQS, TDQS#
DQS, DQS#
A14, A13,
ODT[1:0]
Symbol
CKE[1:0]
CS#[1:0]
CK, CK#
DQ[3:0]
DQ[7:0]
BA[2:0]
RESET#
V
DM
DD
82-Ball and 78-Ball FBGA Ball Descriptions
Output
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by
BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to V
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine
whether burst chop (on-the-fly) will be performed (HIGH = burst length (BL) of 8 or no burst
chop, LOW = burst chop (BC) of 4, burst chop).
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
V
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is
dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding
CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding
CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for external
rank selection on systems with multiple ranks. CS# is considered part of the command code.
CS# is referenced to V
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is
referenced to V
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to V
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to V
Reset: RESET# is an active LOW CMOS input referenced to V
a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
V
Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to V
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to V
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
Power supply: 1.5V ±0.075V.
REFCA
DDQ
. RESET# assertion and desertion are asynchronous.
.
REFDQ
REFDQ
REFDQ
. DM has an optional use as TDQS on the x8.
.
.
REFCA
.
5
REFCA
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REFCA
Ball Assignments and Descriptions
4Gb: x4, x8 TwinDie DDR3 SDRAM
.
REFCA
SS
. The RESET# input receiver is
©2008 Micron Technology, Inc. All rights reserved.
. A12/BC#: When enabled
DDQ
and DC LOW ≤ 0.2 ×
REFCA
.