MT47H128M16RT-25E IT:C Micron Technology Inc, MT47H128M16RT-25E IT:C Datasheet - Page 32

• Manufacturer Part Number: MT47H128M16RT-25E IT:C
• Manufacturer: Micron Technology Inc

Specifications of MT47H128M16RT-25E IT:C

• Lead Free Status / Rohs Status: Compliant

Table 11: DDR2 I
Notes 1–7 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Parameter/Condition
Operating burst read current: All banks
open, continuous burst reads, I
= 4, CL = CL (I
=
HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus in-
puts are switching
Burst refresh current:
fresh command at every
CKE is HIGH, CS# is HIGH between valid com-
mands; Other control and address bus inputs
are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V;
CKE ≤ 0.2V; Other control and address bus in-
puts are floating; Data bus inputs are floating
Operating bank interleave read current:
All bank interleaving reads, I
4, CL = CL (I
t
(I
HIGH between valid commands; Address bus
inputs are stable during deselects; Data bus
inputs are switching (see Table 9 (page 28)
for details)
CK =
DD
t
RAS MAX (I
),
t
t
RCD =
CK (I
DD
DD
t
DD
),
RCD (I
DD
), AL =
t
), AL = 0;
RC =
),
t
RP =
DD
DD
t
t
RCD (I
RC (I
Notes:
); CKE is HIGH, CS# is
Specifications and Conditions (Die Revision C) (Continued)
t
RP (I
t
t
t
CK =
RFC (I
CK =
DD
DD
),
DD
OUT
) - 1 x
t
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
OUT
t
DD
CK (I
RRD =
); CKE is
CK (I
= 0mA; BL =
) interval;
UDQS#. I
operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
DD
DD
DD1
= 0mA; BL
DD
DD
t
DD
CK (I
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
t
); re-
= +1.8V ±0.1V, V
RRD
),
DD4R
t
RAS
DD
DD
);
, and I
values must be met with all combinations of EMR bits 10 and 11.
Symbol Configuration -187E -25E
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
IN
IN
I
I
DD
I
I
I
DD4R
DD6L
DD5
DD6
DD7
DD
DD7
≤ V
≥ V
values must be derated (I
conditions:
IL(AC)max
IH(AC)min
require A12 in EMR1 to be enabled during testing.
DDQ
REF
= +1.8V ±0.1V, V
x4, x8, x16
32
= V
x4, x8
x4, x8
x4, x8
Electrical Specifications – I
x16
x16
x16
DDQ
/2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
C
≤ 85°C:
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
DDL
DD
2Gb: x4, x8, x16 DDR2 SDRAM
= +1.8V ±0.1V, V
limits increase) on IT-option devices when
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
-25
© 2006 Micron Technology, Inc. All rights reserved.
REF
-3E/
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
-3
= V
DD
DDQ
-37E
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
Parameters
/2.
C
≤ +85°C.
-5E
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
Units
mA
mA
mA
mA