MT47H128M16RT-25E IT:C Micron Technology Inc, MT47H128M16RT-25E IT:C Datasheet - Page 124

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MT47H128M16RT-25E IT:C

Manufacturer Part Number
MT47H128M16RT-25E IT:C
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H128M16RT-25E IT:C

Lead Free Status / Rohs Status
Compliant
Figure 77: PRECHARGE Command-to-Power-Down Entry
Figure 78: LOAD MODE Command-to-Power-Down Entry
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Notes:
Note:
Command
Command
Address
Address
1. The earliest precharge power-down entry may occur is at T2, which is 1 ×
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and
3. The earliest precharge power-down entry is at T3, which is after
CK#
CKE
CK#
A10
CKE
CK
PRECHARGE command. Precharge power-down entry occurs prior to
isfied.
CK
Valid
T0
Valid
T0
t RP 2
Valid 1
LM
T1
Single bank
Valid
All banks
124
PRE
T1
vs
1 x
t MRD
t
CK
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
Power-down 1
entry
NOP
T2
2Gb: x4, x8, x16 DDR2 SDRAM
t
Power-down 3
RP met prior to issuing LM command.
entry
NOP
T3
t
CKE (MIN)
T3
Power-Down Mode
© 2006 Micron Technology, Inc. All rights reserved.
t CKE (MIN)
Don’t Care
t
MRD is satisfied.
T4
t
RP (MIN) being sat-
Don’t Care
t
CK after the

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