UDA1345TS NXP Semiconductors, UDA1345TS Datasheet - Page 10

• Manufacturer Part Number: UDA1345TS
• Manufacturer: NXP Semiconductors

Specifications of UDA1345TS

• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.4V
• Single Supply Voltage (max): 3.6V
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
7.10
The UDA1345TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in
Section 7.12.
7.10.1
The pinning definition under L3 microcontroller interface is
given in Table 5.
Table 5 Pinning definition under L3 control
7.10.2
Under L3 control the options are 256, 384 and 512f
7.10.3
The UDA1345TS supports the following data input/output
formats under L3 control:
• I
• MSB-justified serial format with data word length of up to
• LSB-justified serial format with data word lengths of
• Three combined data formats with MSB data output and
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
7.10.4
The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 kΩ as described in Section 7.2. In
L3 microcontroller mode, the gain can be selected via
pin MP5.
When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.
2002 May 28
SYMBOL PIN
20 bits
16, 18 or 20 bits
LSB 16, 18 and 20 bits data input.
Economy audio CODEC
2
MP1
MP2
MP3
MP4
MP5
S-bus with data word length of up to 24 bits
L3 microcontroller mode
P
S
M
ADC
INNING DEFINITION
YSTEM CLOCK
ULTIPLE FORMAT INPUT
13
14
15
20
9
INPUT VOLTAGE CONTROL
OVERFL output
L3MODE input
L3CLOCK input
L3DATA input
ADC 1 V or 2 V (RMS) input control
DESCRIPTION
/
OUTPUT INTERFACE
s
.
10
7.10.5
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (the actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
(11.6 ms at f
infringement.
7.10.6
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.
Table 6 DC cancellation filter characteristics
7.11
The UDA1345TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
7.11.1
The pinning definition under static pin control is given in
Table 7.
Table 7 Pinning definition for static pin control
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
MP1
MP2
MP3
MP4
MP5
SYMBOL PIN
Static pin mode
ITEM
O
DC
P
INNING DEFINITION
VERLOAD DETECTION
s
CANCELLATION FILTER
13
14
15
20
9
= 44.1 kHz). This time-out is reset for each
data input/output setting
3-level pin controlling de-emphasis
and mute
256f
3-level pin to control ADC power mode
and 1 V (RMS) or 2 V (RMS) input
data input/output setting
at 0.00000036f
CONDITIONS
s
at 0.00045f
or 384f
0 − 0.45f
DESCRIPTION
s
(ADC)
system clock
s
(ADC)
s
UDA1345TS
Product specification
s
VALUE (dB)
0.031
none
>110
>40
s
0
cycles