AD5668ARUZ-3 Analog Devices Inc, AD5668ARUZ-3 Datasheet - Page 7

• Manufacturer Part Number: AD5668ARUZ-3
• Description: IC DAC 16BIT LP OCT 5V 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5668ARUZ-3

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Settling Time: 6µs
• Number Of Bits: 16
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 16bit
• Sampling Rate: 95kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 3.6V, 4.5V To 5.5V
• Supply Current: 2mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
V
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Maximum SCLK frequency is 50 MHz at V
DD
1
= 2.7 V to 5.5 V. All specifications T
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
LDAC
LDAC
SYNC
SCLK
V
CLR
OUT
DIN
1
2
Limit at T
V
20
8
8
13
4
4
0
15
13
0
10
15
5
0
300
DD
= 2.7 V to 5.5 V
MIN
t
DD
8
, T
t
10
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
MAX
DB31
MIN
t
13
t
4
to T
t
5
t
15
t
MAX
6
, unless otherwise noted.
t
3
Figure 2. Serial Write Operation
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
t
Rev. E | Page 7 of 28
1
t
2
DD
DB0
) and timed from a voltage level of (V
t
t
14
7
t
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
9
t
11
t
12
AD5628/AD5648/AD5668
IL
+ V
IH
)/2. See Figure 2.