CS43L42-KZZ Cirrus Logic Inc, CS43L42-KZZ Datasheet - Page 35

• Manufacturer Part Number: CS43L42-KZZ
• Description: IC DAC W/HDPN AMP LV 24TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L42-KZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 41mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Other names: 598-1651

DS481PP2
SDATA
SDATA
S D A T A
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 20-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
LRCK
SCLK
LRCK
L R C K
S C L K
SCLK
1
0
0
19 18
Internal SCLK Mode
Internal SCLK Mode
Internal SCLK Mode
17 16
15 14 13 12 11 10
23 22 21 20 19 18
15 14 13 12 11 10
3 2 c lo cks
3 2 c lo cks
Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5
Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3
L e ft C h a n ne l
Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4
L e ft C h a n ne l
L eft C ha nn e l
32 clocks
9
9
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Right Justified, 20-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 40 Cycles per LRCK Period
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
0
0
0
19 18
17 16
15 14 13 12 11 10
23 22 21 20 19 18
15 14 13 12 11 10
External SCLK Mode
External SCLK Mode
External SCLK Mode
R ig h t C h a n n e l
R ig h t C h a n n e l
R ig ht C h ann el
9
9
8
8
7
7
7
6
6
6
5
5
5
4
4
CS43L42
4
3
3
3
2
2
2
1
1
1
0
0
0
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