CS43L42-KZZ Cirrus Logic Inc, CS43L42-KZZ Datasheet - Page 27

• Manufacturer Part Number: CS43L42-KZZ
• Description: IC DAC W/HDPN AMP LV 24TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L42-KZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 41mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Other names: 598-1651

DEM0 and DEM1
(Stand-Alone Mode)
VL
MCLK
SCL/CCLK
(Control Port Mode)
SDA/CDIN
(Control Port Mode)
DS481PP2
4 and 5
6
7
8
9
De-emphasis Control (Input) - Selects the appropriate digital filter to maintain the standard
Note:
Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.
Master Clock (Input) - Frequency must be either 256x, 384x, 512x, 768x or 1024x the input
Serial Control Interface Clock (Input) - Clocks the serial control data into or out of
Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is
15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Fig-
ure 30) When using Internal Serial Clock Mode, Pin 5 is available for de-emphasis control,
DEM1, and all de-emphasis filters are available. When using External Serial Clock Mode,
Pin 5 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is avail-
able. (see Table 9)
sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate
in High Rate Mode (HRM). Note that some multiplication factors require setting the
MCLKDIV bit (see Master Clock DIVIDE ENABLE (mclkdiv)). Tables 10 and 11 illustrate
several standard audio sample rates and the required master clock frequencies.
SDA/CDIN.
the input data line for the control port interface in SPI mode.
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).
* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).
Sample Rate
Sample Rate
DEM1
(kHz)
(kHz)
44.1
44.1
88.2
0
0
1
1
32
48
32
48
64
96
De-emphasis is not available in High-Rate Mode.
DEMO
Internal SCLK
Table 10. HRM Common Clock Frequencies
0
1
0
1
12.2880
11.2896
8.1920
12.2880
11.2896
4.0960
5.6448
6.1440
8.1920
256x
128x
Table 11. BRM Common Clock Frequencies
Table 9. Stand Alone De-Emphasis Control
Disabled
44.1kHz
48kHz
32kHz
DESCRIPTION
18.4320
12.2880
16.9344
384x
12.2880
16.9344
18.4320
6.1440
8.4672
9.2160
192x
MCLK (MHz)
HRM
MCLK (MHz)
16.3840
22.5792
24.5760
BRM
512x
12.2880
16.3840
22.5792
24.5760
11.2896
8.1920
256x*
DEMO
0
1
24.5760
32.7680
36.8640
External SCLK
768x*
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
384x*
DESCRIPTION
CS43L42
44.1 kHz
Disabled
32.7680
45.1584
49.1520
1024x*
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