AD569JNZ Analog Devices Inc, AD569JNZ Datasheet - Page 10

IC DAC 16BIT MONO 28-DIP

AD569JNZ

Manufacturer Part Number
AD569JNZ
Description
IC DAC 16BIT MONO 28-DIP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD569JNZ

Data Interface
Parallel
Settling Time
4µs
Number Of Bits
16
Number Of Converters
1
Voltage Supply Source
Dual ±
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
28-DIP (0.600", 15.24mm)
Resolution (bits)
16bit
Input Channel Type
Parallel
Supply Current
9mA
Digital Ic Case Style
DIP
No. Of Pins
28
Operating Temperature Range
0°C To +70°C
Supply Voltage Range - Analog
± 10.8V To ± 13.2V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
AD569
under worst-case conditions (hex input code 0000), feedthrough
remains below –100 dB at ac reference frequencies up to 10 kHz.
BYPASSING AND GROUNDING RULES
It is generally considered good engineering practice to use bypass
capacitors on the device supply voltage pins and to insert small
valued resistors in the supply lines to provide a measure of decou-
pling between various circuits in a system. For the AD569, bypass
capacitors of at least 4.7 F and series resistors of 10
mended. The supply voltage pins should be decoupled to Pin 18.
NOISE
In high-resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 152 V
(–96 dB). Therefore, the noise floor must remain below this
level in the frequency ranges of interest. The AD569’s noise
spectral density is shown in Figures 17 and 18. The lowband
noise spectrum in Figure 17 shows the 1/f corner frequency at
1.2 kHz and Figure 18 shows the wideband noise to be below
40 nV/ Hz.
Figure 18. Wideband Noise Spectrum
Figure 17. Lowband Noise Spectrum
Figure 16. Multiplying Feedthrough
are recom-
–10–
DIGITAL CIRCUIT CONNECTIONS
The AD569’s truth table appears in Table I. The High Byte En-
able (HBE) and Low Byte Enable (LBE) inputs load the upper
and lower bytes of the 16-bit input when Chip Select (CS) is
valid (low). A similar strobe to Load DAC (LDAC) loads the
16-bit input into the DAC register and completes the DAC up-
date. The DAC register can either be loaded with a separate
write cycle or synchronously with either of the 8-bit registers in
the first rank. A simultaneous update of several AD569s can be
achieved by controlling their LDAC inputs with a single control
signal.
CS
1
X
0
0
0
0
All four control inputs latches are level-triggered and active low.
When the DAC register is loaded directly from a bus, the data at
the digital inputs will be reflected in the output any time CS,
LDAC, LBE and HBE are low. Should this not be the desired
case, bring LDAC (or HBE or LBE) high before changing the
data. Alternately, use a second write cycle to transfer the data to
the DAC register or delay the write strobe pulse until the appro-
priate data is valid. Be sure to observe the appropriate data
setup and hold times (see Timing Characteristics).
Whenever possible, the write strobe signal should be applied to
HBE and LBE with the AD569’s decoded address applied to
CS. A minimum pulse width of 60 ns at HBE and LBE allows
the AD569 to interface to the fastest microprocessors. Actually,
data can be latched with narrower pulses, but the data setup and
hold times must be lengthened.
16-Bit Microprocessor Interfaces
Since 16-bit microprocessors supply the AD569’s complete 16-
bit input in one write cycle, the DAC register is often unneces-
sary. If so, it should be made transparent by grounding LDAC.
The DAC’s decoded address should be applied to CS, with the
write strobe applied to HBE and LBE as shown in the 68000 in-
terface in Figure 19.
HBE
X
1
0
1
1
0
Figure 19. AD569/68000 Interface
LBE
X
1
1
0
1
0
Table I. AD569 Truth Table
LDAC
X
1
1
1
0
0
OPERATION
No Operation
No Operation
Enable 8 MSBs of First Rank
Enable 8 LSBs of First Rank
Enable 16-Bit DAC Register
All Latches Transparent
REV. A

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