AD5724RBREZ Analog Devices Inc, AD5724RBREZ Datasheet - Page 20

• Manufacturer Part Number: AD5724RBREZ
• Description: IC DAC 12BIT DSP/SRL 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ

• Data Interface: Serial
• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 12bit
• Sampling Rate: 1.1MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 2.5mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5724R/AD5734R/AD5754R
THEORY OF OPERATION
The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit,
serial input, unipolar/bipolar, voltage output DACs. They
operate from single supply voltages of +4.5 V to +16.5 V or dual
supply voltages of ±4.5 V to ±16.5 V. In addition, the parts have
software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V,
±10 V, and ±10.8 V. Data is written to the AD5724R/AD5734R/
AD5754R in a 24-bit word format via a 3-wire serial interface.
The devices also offer an SDO pin to facilitate daisy chaining or
readback.
The AD5724R/AD5734R/AD5754R incorporate a power-on
reset circuit to ensure that the DAC registers power up loaded
with 0x0000. When powered on, the outputs are clamped to 0 V
via a low impedance path. The parts also feature on-chip
reference and reference buffers.
ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 44 shows a block diagram of the DAC
architecture. The reference input is buffered before being applied
to the DAC.
The resistor string structure is shown in Figure 45. It is a string
of resistors, each of value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
DAC REGISTER
Figure 44. DAC Architecture Block Diagram
RANGE CONTROL
RESISTOR
REF (–)
REF (+)
STRING
REFIN
GND
OUTPUT
CONFIGURABLE
OUTPUT
AMPLIFIER
V
OUT
x
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Output Amplifiers
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 4000 pF to GND. The source and sink
capabilities of the output amplifiers can be seen in Figure 24.
The slew rate is 3.5 V/μs with a full-scale settling time of 10 μs.
Reference Buffers
The AD5724R/AD5734R/AD5754R can operate with either an
external or internal reference. The reference input has an input
range of 2 V to 3 V with 2.5 V for specified performance. This
input voltage is then buffered before it is applied to the DAC cores.
SERIAL INTERFACE
The AD5724R/AD5734R/AD5754R are controlled over a
versatile 3-wire serial interface that operates at clock rates up
to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE™,
and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits. The timing diagram for this operation is shown in Figure 2.
R
R
R
R
R
REFIN
Figure 45. Resistor String Structure
TO OUTPUT
AMPLIFIER