MCP4912-E/ST Microchip Technology, MCP4912-E/ST Datasheet - Page 27

• Manufacturer Part Number: MCP4912-E/ST
• Description: DAC 10BIT DUAL W/SPI 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4912-E/ST

• Number Of Converters: 2
• Settling Time: 4.5µs
• Package / Case: 14-TSSOP
• Number Of Bits: 10
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Dac Outputs: 2
• Resolution: 10 bit
• Interface Type: SPI
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Supply Current: 350 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
The MCP4902/4912/4922 family of devices are gen-
eral purpose DACs intended to be used in applications
where a precision with low-power and moderate
bandwidth is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor Calibration
• Digitally-Controlled Multiplier/Divider
• Portable Instrumentation (Battery Powered)
• Motor Control Feedback Loop
6.1
The MCP4902/4912/4922 utilizes a 3-wire synchro-
nous serial protocol to transfer the DAC’s setup and
output values from the digital source. The serial proto-
col can be interfaced to SPI or Microwire peripherals
that is common on many microcontroller units (MCUs),
including Microchip’s PIC
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the two DAC
outputs. By bringing down the LDAC pin to “low”, all
DAC input codes and settings in the two DAC input
registers are latched into their DAC output registers at
the same time. Therefore, both DAC
outputs are updated at the same time.
shows an example of the pin connections. Note that the
LDAC pin can be tied low (V
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16-clock transmission has been received and CS pin
has been raised.
6.2
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply’s traces from various
events such as digital switching or as a result of
changes on the DAC’s output. The bypass capacitor
helps to minimize the effect of these noise sources.
Figure 6-1
this example, two bypass capacitors are used in
parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).
These capacitors should be placed as close to the
device power pin (V
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
 2010 Microchip Technology Inc.
SS
should reside on the analog plane.
TYPICAL APPLICATIONS
Digital Interface
Power Supply Considerations
illustrates an appropriate bypass strategy. In
DD
) as possible (within 4 mm).
®
MCUs and dsPIC
SS
) to reduce the required
A
and DAC
Figure 6-1
®
DSCs.
DD
and
B
FIGURE 6-1:
Diagram.
6.3
Inductively-coupled AC transients and digital switching
noises can degrade the input and output signal
integrity, and potentially reduce the device perfor-
mance. Careful board layout will minimize these effects
and increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
C2 = 0.1 µF
C1 = 10 µF
V
V
V
V
MCP4902/4912/4922
REFA
OUTA
REFB
OUTB
C1
V
AV
Layout Considerations
DD
SS
SDI
V
V
V
V
REFA
OUTA
REFB
OUTB
C1
Typical Connection
V
AV
DD
SS
C2
SDI
DS22250A-page 27
LDAC
CS
SDO
SCK
CS
C1
0
1
V
V
DD
SS
C2