MAX530BCAG+ Maxim Integrated Products, MAX530BCAG+ Datasheet - Page 15

• Manufacturer Part Number: MAX530BCAG+
• Description: IC DAC 12BIT PAR/VOLT I/O 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX530BCAG+

• Settling Time: 25µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 250 uA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

As with any amplifier, the MAX530’s output op amp offset
can be positive or negative. When the offset is positive, it
is easily accounted for. However, when the offset is nega-
tive, the output cannot follow linearly when there is no
negative supply. In that case, the amplifier output (VOUT)
remains at ground until the DAC voltage is sufficient to
overcome the offset and the output becomes positive.
The resulting transfer function is shown in Figure 13.
Normally, linearity is measured after allowing for zero
error and gain error. Since, in single-supply operation,
the actual value of a negative offset is unknown, it can-
not be accounted for during test. In the MAX530, linear-
ity and gain error are measured from code 11 to code
4095 (see Note 2 under Electrical Characteristics ). The
output amplifier offset does not affect monotonicity, and
these DACs are guaranteed monotonic starting with
code zero. In dual-supply operation, linearity and gain
error are measured from code 0 to 4095.
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital ground
planes. Wire-wrap boards are not recommended. The
two ground planes should be connected together at the
low-impedance power-supply source.
AGND and REFGND should be connected together,
and then to DGND at the chip. For single-supply appli-
Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)
__________Applications Information
33µF
______________________________________________________________________________________
REFIN
REFOUT
AGND
DGND
REFGND
and Ground Management
Power-Supply Bypassing
MAX530
Single-Supply Linearity
-5V
+5V
ROFS
VOUT
RFB
+5V, Low-Power, Parallel-Input,
V
OUT
Voltage-Output, 12-Bit DAC
Figure 12. Four-Quadrant Multiplying Circuit
cations, connect V
ground connection may be achieved by connecting
the AGND, REFGND, and DGND pins together and
connecting that point to the system analog ground
plane. If DGND is connected to the system digital
ground, digital noise may get through to the DAC’s ana-
log portion.
Bypass V
0.1µF ceramic capacitor connected between V
AGND (and between V
capacitors with short leads close to the device.
High-speed data at any of the digital input pins may
couple through the DAC package and cause internal
stray capacitance to appear as noise at the DAC out-
put, even though LDAC and CS are held high (see
Typical Operating Characteristics ). This digital
feedthrough is tested by holding
and toggling the data inputs from all 1s to all 0s.
Because of internal stray capacitance, higher-frequen-
cy analog input signals at REFIN may couple to the
output, even when the input digital code is all 0s, as
shown in the Typical Operating Characteristics graph
Analog Feedthrough vs. Frequency. It is tested by set-
ting CLR to low (which sets the DAC latches to all 0s)
and sweeping REFIN.
DD
(and V
REFGND
AGND
DGND
SS
SS
to AGND at the chip. The best
in dual-supply mode) with a
MAX530
SS
V
-5V
+5V
V
SS
DD
and AGND). Mount the
AC Considerations
Analog Feedthrough
REFIN
VOUT
Digital Feedthrough
ROFS
RFB
LDAC and CS high
REFIN
V
OUT
DD
and
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