MAX5104CEE+ Maxim Integrated Products, MAX5104CEE+ Datasheet - Page 8

• Manufacturer Part Number: MAX5104CEE+
• Description: IC DAC 12BIT DUAL SER 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5104CEE+

• Settling Time: 15µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 0.5 mA
• Voltage Reference: 1.4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
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Figure 5. Serial-Interface Timing Diagram
MSB...................................................................................LSB
Address Bits
_______________________________________________________________________________________
1 Address/2 Control Bits
A0
SCLK
DIN
MAX5104
CS
A0
Control Bits
SCLK
16 Bits of Serial Data
C1, C0
DIN
CS
1
C1
C0
MSB...Data Bits...LSB
D11.......................D0
D11
CPOL = 0, CPHA = 0
12 Data Bits
MOSI
SCK
I/O
D10
SPI/QSPI
D9
PORT
+5V
SS
D8
Sub
D7
Bit
S0
0
8
D6
The MAX5104’s digital inputs are double buffered,
which allows any of the following: loading the input reg-
ister(s) without updating the DAC register(s), updating
the DAC register(s) from the input register(s), or updating
the input and DAC registers concurrently. The address
and control bits allow the DACs to act independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with CS low during
this period. The address and control bits determine
which register will be updated, and the state of the reg-
isters when exiting power-down. The 3-bit address/con-
trol determines the following:
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data; otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maximum
clock frequency guaranteed for proper operation is
10MHz. Figure 6 shows a more detailed timing diagram
of the serial interface.
• Registers to be updated
• Clock edge on which data is to be clocked out via the
• State of the user-programmable logic output
• Configuration of the device after power-down
9
serial-data output (DOUT)
D5
D4
D3
D2
D1
D0
S0
16
COMMAND
EXECUTED