MAX5104CEE+ Maxim Integrated Products, MAX5104CEE+ Datasheet - Page 10

• Manufacturer Part Number: MAX5104CEE+
• Description: IC DAC 12BIT DUAL SER 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5104CEE+

• Settling Time: 15µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 0.5 mA
• Voltage Reference: 1.4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
The serial-data output, DOUT, is the internal shift register’s
output. DOUT allows for daisy chaining of devices and
data readback. The MAX5104 can be programmed to
shift data out of DOUT on SCLK’s falling edge (Mode 0)
or on the rising edge (Mode 1). Mode 0 provides a lag
of 16 clock cycles, which maintains compatibility with
SPI/QSPI and MICROWIRE interfaces. In Mode 1, the
output data lags 15.5 clock cycles. On power-up, the
device defaults to Mode 0.
User-programmable logic output (UPO) allows an external
device to be controlled through the serial interface
(Table 1), thereby reducing the number of microcontroller
I/O pins required. On power-up, UPO is low.
The power-down lockout (PDL) pin disables software
shutdown when low. When in power-down, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to power-down. PDL can also be
used to asynchronously wake up the device.
Any number of MAX5104s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
Since the MAX5104’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines the
time required to discharge/charge a capacitive load.
See the digital output V
Electrical Characteristics .
Figure 8 shows an alternate method of connecting several
MAX5104s. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy chain.
More I/O lines are required in this configuration because
a dedicated chip-select input (CS) is required for each IC.
Figure 9 shows the MAX5104 configured for unipolar,
rail-to-rail operation with a gain of +2V/V. The MAX5104
can produce a 0 to 4.096V output with a 2.048V reference
(Figure 9). Table 2 lists the unipolar output codes. An
offset to the output can be achieved by connecting a
voltage to OS_, as shown in Figure 10. By applying
V
and (1V + V
The MAX5104 can be configured for a bipolar output
(Figure 11). The output voltage is given by the equation
(OS_ = AGND):
10
__________Applications Information
OS_
______________________________________________________________________________________
= -1V, the output values will range between 1V
REF
User-Programmable Logic Output
· 2).
Power-Down Lockout Input
OH
Daisy-Chaining Devices
and V
Serial-Data Output
OL
Unipolar Output
specifications in the
Bipolar Output
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
Figure 10. Setting OS_ for Output Offset
Table 2. Unipolar Code Table (Gain = +2)
Note: ( ) are for the sub-bit.
MSB
1 1 1 1 1 1 1 1 11 1 1 ( 0 )
1 0 0 0 0 0 0 0 00 0 1 ( 0 )
1 0 0 0 0 0 0 0 00 0 0 ( 0 )
0 1 1 1 1 1 1 1 11 1 1 ( 0 )
0 0 0 0 0 0 0 0 0 0 0 1 ( 0 )
0 0 0 0 0 0 0 0 00 0 0 ( 0 )
DAC CONTENTS
GAIN = +2V/V
REF_
REF_
DAC _
DAC_
MAX5104
MAX5104
LSB
AGND
AGND
+5V/+3V
+5V/+3V
V
V
DD
+V
DD
REF
ANALOG OUTPUT
+V
+V
+V
+V
REF
DGND
REF
REF
REF
R
R
DGND
R
R
2048
4096
2049
4096
2047
4096
4096
0V
4095
4096
OS_
OS_
1
OUT_
2
OUT_
2
2
2
2
V
V
REF
OS