AD9777BSVZ Analog Devices Inc, AD9777BSVZ Datasheet - Page 5

• Manufacturer Part Number: AD9777BSVZ
• Description: IC DAC 16BIT DUAL 160MSPS 80TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9777BSVZ

• Data Interface: Parallel
• Settling Time: 11ns
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 400MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 3.1V To 3.5V
• Supply Current: 72.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9777-EBZ - BOARD EVALUATION FOR AD9777
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SPECIFICATIONS
DC SPECIFICATIONS
T
Table 1.
Parameter
RESOLUTION
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
REFERENCE OUTPUT
REFERENCE INPUT
TEMPERATURE COEFFICIENTS
POWER SUPPLY
OPERATING RANGE
1
2
3
4
5
Measured at I
Nominal full-scale current, I
Use an external amplifier to drive any external load.
100 MSPS f
400 MSPS f
MIN
DC Accuracy
Offset Error
Gain Error (with Internal Reference)
Gain Matching
Full-Scale Output Current
Output Compliance Range
Output Resistance
Output Capacitance
Gain, Offset Cal DACs, Monotonicity Guaranteed
Reference Voltage
Reference Output Current
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
Offset Drift
Gain Drift (with Internal Reference)
Reference Voltage Drift
AVDD
CLKVDD (PLL OFF)
CLKVDD (PLL ON)
DVDD
Power Supply Rejection Ratio—AVDD
Integral Nonlinearity
Differential Nonlinearity
Voltage Range
Analog Supply Current (I
I
Voltage Range
Clock Supply Current (I
Clock Supply Current (I
Voltage Range
Digital Supply Current (I
Nominal Power Dissipation
P
P
to T
AVDD
DIS
DIS
5
in PWDN
MAX
in SLEEP Mode
DAC
DAC
OUTA
, f
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
with f
DATA
1
driving a virtual ground.
= 50 MSPS, f
OUT
= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
OUTFS
, is 32× the I
S
CLKVDD
CLKVDD
2
/2 modulation, PLL enabled.
3
DVDD
AVDD
4
)
)
)
)
4
4
4
REF
current.
Rev. C | Page 5 of 60
Min
16
−6.5
−0.025
−1.0
−1
2
−1.0
1.14
0.1
3.1
3.1
3.1
−40
OUTFS
= 20 mA, unless otherwise noted.
Typ
±6
±3
±0.01
±0.1
200
3
1.20
100
7
0.5
0
50
±50
3.3
72.5
23.3
3.3
8.5
23.5
3.3
34
380
1.75
6.0
±0.4
Max
+6.5
+0.025
+1.0
+1
20
+1.25
1.26
1.25
3.5
76
26
3.5
10.0
3.5
41
410
+85
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
mA
mA
V
mA
mA
V
mA
mW
W
mW
% of FSR/V
°C
AD9777