AD9744ACPZ Analog Devices Inc, AD9744ACPZ Datasheet - Page 16

• Manufacturer Part Number: AD9744ACPZ
• Description: IC DAC 14BIT 210MSPS 32-LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9744ACPZ

• Data Interface: Parallel
• Settling Time: 11ns
• Number Of Bits: 14
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 210MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Voltage Range - Digital: 2.7V To 3.6V
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Integral Nonlinearity Error: ±5LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LFCSP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9744ACP-PCBZ - BOARD EVAL FOR AD9744ACP
• Lead Free Status / Rohs Status: Compliant

AD9744
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the time at
which the input data changes. The AD9744 is rising edge trig-
gered, and so exhibits dynamic performance sensitivity when
the data transition is close to this edge. In general, the goal
when applying the AD9744 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 30 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock place-
ment, while at higher rates, more care must be taken.
Sleep Mode Operation
The AD9744 has a power-down function that turns off the out-
put current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and tempera-
ture range. This mode can be activated by applying a logic level
1 to the SLEEP pin. The SLEEP pin logic threshold is equal to
0.5 Ω AVDD. This digital input also contains an active pull-
down circuit that ensures that the AD9744 remains enabled if
this input is left disconnected. The AD9744 takes less than 50 ns
to power down and approximately 5 µs to power back up.
Figure 30. SFDR vs. Clock Placement @ f
CLK+
CLK–
75
70
65
60
55
50
45
40
35
–3
50MHz SFDR
50Ω
Figure 29. Clock Termination in PECL Mode
–2
V
TT
= 1.3V NOM
20MHz SFDR
50Ω
–1
CLOCK
RECEIVER
AD9744
ns
0
OUT
50MHz SFDR
1
= 20 MHz and 50 MHz
TO DAC CORE
2
3
Rev. B | Page 16 of 32
POWER DISSIPATION
The power dissipation, P
eral factors that include:
•
•
•
•
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
digital input waveform, f
Figure 32 shows I
output ratios (f
DVDD = 3.3 V.
The power supply voltages (AVDD, CLKVDD, and
DVDD)
The full-scale current output I
The update rate f
The reconstructed digital input waveform
35
30
25
20
15
10
20
18
16
14
12
10
0
8
6
4
2
0
0.01
2
4
CLOCK
OUT
Figure 32. I
AVDD
DVDD
/f
. Conversely, I
CLOCK
6
, and the digital supply current, I
CLOCK
as a function of full-scale sine wave
Figure 31. I
) for various update rates with
DVDD
D
CLOCK
8
RATIO (f
, of the AD9744 is dependent on sev-
OUTFS
vs. Ratio @ DVDD = 3.3 V
I
125MSPS
210MSPS
165MSPS
OUTFS
, and digital supply DVDD.
65MSPS
10
, as shown in Figure 31, and is
AVDD
0.1
OUT
DVDD
(mA)
/f
OUTFS
12
vs. I
CLOCK
OUTFS
is dependent on both the
14
)
16
18
DVDD
20
1
. I
AVDD