CS4392-KZZ Cirrus Logic Inc, CS4392-KZZ Datasheet - Page 9

• Manufacturer Part Number: CS4392-KZZ
• Description: IC DAC 24BIT 192KHZ W/VC 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4392-KZZ

• Package / Case: 20-TSSOP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 150mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 200 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 150 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4392 - EVALUATION BOARD FOR CS4392
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1065-5

3. APPLICATIONS
3.1
1) Hold
2) Bring
3.2
1) Hold
2) Bring
3) Write 30h to register 05h within 10 ms cycles following the release of RST. If after 10ms the control
4) The desired register settings can be loaded while keeping the PDN bit set to 1.
5) Set the PDN bit to 0. This will initiate the power-up sequence which requires approximately 10 µS.
3.3
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter as seen in Figure 3. An alternate configuration
can be seen on the CDB4392. This alternate filter configuration accounts for the differing AC loads on the
+ and - differential output pins which are normally present in a circuit like Figure 3. It also shows an AC
coupling configuration which reduces the number of required AC coupling capacitors to 2 caps per chan-
nel. The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be
AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation
for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the
external analog circuitry.
DS459PP3
port is reset to its default settings and FILT+ will remain low.
accessible.
port has not been initiated with this command, the device will enter stand-alone mode. The CPEN bit,
however, may be written at any time after 10ms. It is recommended to write CPEN before 10ms in or-
der to reduce the possibility of any extraneous click or pop noise from occurring.
Recommended Power-up Sequence for Hardware Mode
Recommended Power-up Sequence and Access to Control Port Mode
Analog Output and Filtering
RST
RST
RST
RST
Aout -
Aout +
low until the power supplies, master, and left/right clocks are stable.
low until the power supply, master, and left/right clocks are stable. In this state, the control
high. After 10ms the device will begin normal operation.
high. The device will remain in a low power state with FILT+ low and the control port is
10 uF
10 uF
2700 pF
2700 pF
3.01k
3.01k
Figure 3. CS4392 Output Filter
R17
3.32k
1.58k
1.58k
C10
680 pF
2
3
-
+
3.32k
680 pF
1
10 uF
560
47k
Analog_Out
CS4392
9