CS4392-KZZ Cirrus Logic Inc, CS4392-KZZ Datasheet - Page 15

• Manufacturer Part Number: CS4392-KZZ
• Description: IC DAC 24BIT 192KHZ W/VC 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4392-KZZ

• Package / Case: 20-TSSOP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 150mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 200 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 150 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4392 - EVALUATION BOARD FOR CS4392
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1065-5

DS459PP3
4.0.2b
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I
must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 4.1) if an I
operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I
essary to initiate a STOP condition and follow the procedure detailed from steps 1 and 2
from the I
reads from other registers are desired, initiate a STOP condition to the bus.
S D A
S C L
N o te : If o p eration is a w rite , th is byte con ta in s the M e m o ry A d dress P o inter, M A P .
2
S ta rt
C Write instructions followed by step 1 of the I
I
2
C Read
0 01 0 00
Figure 8. Control Port Timing, I
A D D R
A D 0
R /W
A C K
2
C bus followed by the address byte. The upper 6 bits
2
D A T A
1 -8
C reads from other registers are desired, it is nec-
N ote 1
A C K
2
C Mode
D A TA
1-8
2
C Read section. If no further
A C K
Stop
2
C read is the first
CS4392
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