CS4361-CZZ Cirrus Logic Inc, CS4361-CZZ Datasheet - Page 9

• Manufacturer Part Number: CS4361-CZZ
• Description: IC DAC STER 6CH 103DB 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4361-CZZ

• Package / Case: 20-TSSOP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 455mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 85 C
• Maximum Power Dissipation: 455 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1153 - BOARD EVAL FOR CS4361428-1454 - SOCKET ADAPTER FOR CY2077FZ
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1057-5

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate All MCLK/LRCK ratios combined
(Note 11)
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Duty Cycle
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
SCLK rising to LRCK edge
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
11. Not all sample rates are supported for all clock ratios. See table
12. In Internal SCLK Mode, the duty cycle must be 50%
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
page 12
MCLK/LRCK ratio. (See
MCLK / LRCK = 768, 384, 192, or 96
for supported ratios and frequencies.
Parameters
256x, 384x, 1024x
Figures
256x, 384x
512x, 768x
128x, 192x
128x, 192x
(Note 12)
(Note 13)
7-10)
64x, 96x
Confidential Draft
1152x
2/12/08
Symbol
t
t
t
t
t
t
sclkw
sclkh
t
t
t
t
t
sdlrs
sclkr
sdlrs
sclkl
Fs
slrd
sdh
sdh
sdh
slrs
±
--------------------- -
(
--------------------- -
(
--------------------- -
(
512
384
512
1/2 MCLK period.
10
10
10
0.512
--------------- -
SCLK
Min
100
168
)Fs
9
)Fs
45
84
42
30
50
45
20
20
45
20
20
20
20
)Fs
9
9
10
2
2
-
-
9
+
+
+
15
15
10
“Common Clock Frequencies” on
tsclkw
----------------- -
Typ
50
50
50
-
-
-
-
-
-
-
-
-
2
-
-
-
Max
216
134
108
216
216
50
55
54
67
34
55
55
-
-
-
-
-
-
-
-
-
-
-
-
CS4361
Units
MHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
%
%
%
%
9