AD5312BRMZ Analog Devices Inc, AD5312BRMZ Datasheet - Page 14
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AD5312BRMZ
Manufacturer Part Number
AD5312BRMZ
Description
IC DAC 10BIT DUAL R-R 10-MSOP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5302ARMZ.pdf
(24 pages)
Specifications of AD5312BRMZ
Data Interface
Serial
Settling Time
6µs
Number Of Bits
10
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
2.5mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Resolution (bits)
10bit
Sampling Rate
143kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
2.5V To 5.5V
Supply Current
300µA
Digital Ic Case Style
SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5312BRMZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5302/AD5312/AD5322
FUNCTIONAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They contain reference buffers and output
buffer amplifiers, and are written to via a 3-wire serial interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/μs. Each DAC is provided with a separate
reference input, which can be buffered to draw virtually no
current from the reference source, or unbuffered to give a
reference input range from GND to V
programmable power-down modes, in which one or both DACs
can be turned off completely with a high impedance output, or
the output can be pulled low by an on-chip resistor.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register:
N = DAC resolution.
RESISTOR STRING
The resistor-string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
REGISTER
INPUT
0 to 255 for AD5302 (8 bits)
0 to 1023 for AD5312 (10 bits)
0 to 4095 for AD5322 (12 bits)
V
OUT
=
V
Figure 28. Single DAC Channel Architecture
REF
2
REGISTER
N
×
DAC
D
REFERENCE
BUFFER
REF
RESISTOR
STRING
V
pin provides the reference
REF
A
DD
. The devices have three
OUTPUT BUFFER
SWITCH
CONTROLLED
BY CONTROL
LOGIC
AMPLIFIER
V
Rev. C | Page 14 of 24
OUT
A
DAC REFERENCE INPUTS
There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as
unbuffered. The advantage of the buffered input is the high
impedance it presents to the voltage source driving it.
However, if the unbuffered mode is used, the user can have a
reference voltage as low as GND and as high as V
there is no restriction due to headroom and footroom of the
reference amplifier. If there is a buffered reference in the circuit
(for example, REF192), there is no need to use the on-chip
buffers of the AD5302/AD5312/AD5322. In unbuffered mode,
the impedance is still large (180 kΩ per reference input).
The buffered/unbuffered option is controlled by the BUF bit in
the control word (see the Serial Interface section for a
description of the register contents).
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to V
It is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and V
amplifier can be seen in Figure 16.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs. See Figure 21.
POWER-ON RESET
The AD5302/AD5312/AD5322 are provided with a power-on
reset function to power them up in a defined state. The power-
on state is
•
•
•
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
Normal operation
Reference inputs unbuffered
Output voltage set to 0 V
DD
. The source and sink capabilities of the output
R
R
R
R
R
DD
Figure 29. Resistor String
– 0.001 V when the reference is V
TO OUTPUT
AMPLIFIER
DD
because
DD
.