CS4351-CZZ Cirrus Logic Inc, CS4351-CZZ Datasheet - Page 21

• Manufacturer Part Number: CS4351-CZZ
• Description: IC DAC STER 112DB 192KHZ 20TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4351-CZZ

• Package / Case: 20-TSSOP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 354mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V/12 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 354 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1152 - BOARD EVAL FOR CS4351 DAC
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1055-5

DS566F1
4.9.3
4.9.2.2
To read from the device, follow the procedure below while adhering to the control port Switching Specifica-
tions.
4.9.3.1
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see
the device.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read,
then initiate a STOP condition to the bus.
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the
I²C Write instructions followed by step 1 of the I²C Read section. If no further reads from other reg-
isters are desired, initiate a STOP condition to the bus.
Figure 10
Section
I²C Read
SPI Write
S C L
S D A
NOTE: If operation is a write, this byte contains the M em ory Address Pointer, MAP. If
operation is a read, this byte contains the data of the register pointed to by the MAP.
8.
for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
S ta rt
100110
Figure 9. Control Port Timing, I²C Mode
AD0
R/W
Section
ACK
4.10.2) if an I²C read is the first operation performed on
DATA
1-8
NOTE
ACK
DATA
1-8
ACK
Stop
CS4351
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