MCP4922-E/SL Microchip Technology, MCP4922-E/SL Datasheet - Page 18

• Manufacturer Part Number: MCP4922-E/SL
• Description: IC DAC 12BIT DUAL W/SPI 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4922-E/SL

• Number Of Converters: 2
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Settling Time: 4.5µs
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resolution: 12 bit
• Interface Type: Serial (3-Wire, SPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP4921/4922
5.0
5.1
The MCP492X family is designed to interface directly
with the Serial Peripheral Interface (SPI) port, available
on many microcontrollers, and supports Mode 0,0 and
Mode 1,1. Commands and data are sent to the device
via the SDI pin, with data being clocked-in on the rising
edge of SCK. The communications are unidirectional
and, thus, data cannot be read out of the MCP492X.
The CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 details the input registers used to config-
ure and load the DAC
Figure 1-1 and Section 1.0 “Electrical Characteris-
tics” AC Electrical Characteristics table for detailed
input and output timing specifications for both Mode 0,0
and Mode 1,1 operation.
REGISTER 5-1:
DS21897A-page 18
bit 15
bit 14
bit 13
bit 12
bit 11-0
Upper Half:
bit 15
Legend
R = Readable bit
-n = Value at POR
W-x
A/B
SERIAL INTERFACE
Overview
A/B: DAC
1
0
BUF: V
1
0
GA: Output Gain Select bit
1
0
SHDN: Output Power Down Control bit
1
0
D11:D0: DAC Data bits
12 bit number “D” which sets the output value. Contains a value between 0 and 4095.
= Write to DAC
= Write to DAC
= Buffered
= Unbuffered
= 1x (V
= 2x (V
= Output Power Down Control bit
= Output buffer disabled, Output is high impedance
BUF
W-x
Lower Half:
bit 7
REF
A
OUT
OUT
A
W-x
WRITE COMMAND REGISTER
D7
Input Buffer Control bit
or DAC
and DAC
= V
= 2 * V
B
A
REF
W-x
B
GA
Select bit
REF
B
* D/4096)
registers. Refer to
W-x
D6
W = Writable bit
1 = bit is set
* D/4096)
SHDN
W-0
W-x
D5
W-x
D11
W-x
D4
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
5.2
The write command is initiated by driving the CS pin
low, followed by clocking the four configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to
be latched into the selected DAC’s input registers. The
MCP492X utilizes a double-buffered latch structure to
allow both DAC
syncronized with the LDAC pin, if desired. Upon the
LDAC pin achieving a low state, the values held in the
DAC’s input registers are transferred into the DACs’
output registers. The outputs will transition to the value
and held in the DAC
All writes to the MCP492X are 16-bit words. Any
clocks past 16 will be ignored. The most significant
four bits are configuration bits. The remaining 12 bits
are data bits. No data can be transferred into the
device with CS high. This transfer will only occur if 16
clocks have been transferred into the device. If the ris-
ing edge of CS occurs prior, shifting of data into the
input registers will be aborted.
D10
W-x
Write Command
W-x
D3
W-x
D9
A
’s and DAC
X
register.
W-x
D2
 2004 Microchip Technology Inc.
x = bit is unknown
W-x
D8
bit 8
B
W-x
D1
’s outputs to be
W-x
D0
bit 0