MCP4728-E/UN Microchip Technology, MCP4728-E/UN Datasheet - Page 28

• Manufacturer Part Number: MCP4728-E/UN
• Description: IC DAC 12BIT W/I2C 10-MSOP
• Manufacturer: Microchip Technology

Specifications of MCP4728-E/UN

• Number Of Converters: 4
• Settling Time: 6µs
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Number Of Bits: 12
• Data Interface: I²C
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: I2C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 110 mA
• Voltage Reference: 2.048 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP4728EV - BOARD EVAL 12BIT 4CH DAC MCP4728
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP4728
4.10
Each channel has two modes of operation: (a) Normal
mode where analog voltage is available and (b)
Power-Down mode which turns off most of the internal
circuits for power savings.
The user can select the operating mode of each
channel individually by setting the Power-Down
selection bits (PD1 and PD0). For example, the user
can select Normal mode for channel A while selecting
Power-Down mode for all other channels.
See
Registers and EEPROM”
writing the power-down bits.
Most of the internal circuit in the powered down
channel are turned off. However, the internal voltage
reference circuit is not affected by the Power-Down
mode. The internal voltage reference circuit is turned
off only if all channels select external reference (V
= V
Device actions during Power-Down mode:
• The powered down channel stays in a
• No analog voltage output at the powered down
• The output (V
• The contents of both the DAC registers and
• Draws less than 40 nA (typical) when all four
Circuits that are not affected during Power-Down
mode:
• The I
• The internal voltage reference circuit stays
DS22187E-page 28
power-saving condition by turning off most of its
circuits
channel
channel is switched to a known resistive load. The
value of the resistive load is determined by the
state of the Power-Down bits (PD1 and PD0).
Table 4-7
bit settings
EEPROM are not changed
channels are powered down and V
as the voltage reference
order to receive any command from the Master
turned-on if it is selected as reference by at least
one channel
DD
).
Section 5.6 “Write Commands for DAC
2
C serial interface circuits remain active in
Normal and Power-Down Modes
shows the outcome of the Power-Down
OUT
) pin of the powered down
for more details on the
DD
is selected
REF
Exiting Power-Down Mode:
The device exits Power-Down mode immediately by
the following commands:
• Any write command for normal mode. Only
• I
• I
When the DAC operation mode is changed from the
Power-Down to Normal mode, there will be a time
delay until the analog output is available. Typical time
delay for the output voltage is approximately 4.5 µs.
This time delay is measured from the acknowledge
pulse of the I
beginning of the analog output (V
is not included in the output settling time specification.
See
more details.
TABLE 4-7:
FIGURE 4-1:
Power-Down Mode.
Note 1:
selected channel is affected
channels are affected
conditional case. The device exits Power-Down
mode, depending on the Power-Down bit settings
in EEPROM as the configuration bits and DAC
input codes are uploaded from EEPROM. All
channels are affected
2
PD1
Resistor String DAC
2
C General Call Reset Command. This is a
0
0
1
1
C General Call Wake-Up Command. All
Section 2.0 “Typical Performance Curves”
OP
Amp
In Power-Down mode: V
most of internal circuits in the selected
channel are disabled.
PD0
Control Circuit
Power-Down
2
0
1
0
1
C serial communication command to the
POWER-DOWN BITS
Normal Mode
1 kΩ resistor to ground
100 kΩ resistor to ground
(Note
500 kΩ resistor to ground
(Note
Output Stage for
© 2010 Microchip Technology Inc.
Resistive
Load
1)
1)
Function
OUT
1 kΩ
OUT
). This time delay
is off and
100 kΩ 500 kΩ
(Note
V
OUT
1)
for