X9400WV24I-2.7T1 Intersil, X9400WV24I-2.7T1 Datasheet

IC XDCP QUAD 64-TAP 10K 24-TSSOP

X9400WV24I-2.7T1

Manufacturer Part Number
X9400WV24I-2.7T1
Description
IC XDCP QUAD 64-TAP 10K 24-TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of X9400WV24I-2.7T1

Taps
64
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
• Standby current < 1µA max
• System V
• Analog V
• 10kΩ, 2.5kΩ end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
operations of the potentiometer
potentiometer
power-up.
register
HOLD
SCK
WP
SO
CS
V
V
V+
A0
A1
V-
SI
CC
SS
Interface
Circuitry
Control
+
CC
and
/V
: 2.7V to 5.5V operation
: -5V to +5V
Data
®
8
1
Data Sheet
R0 R1
R2 R3
R0 R1
R2 R3
Register
Register
Counter
Counter
(WCR)
(WCR)
Wiper
Wiper
Pot 0
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Resistor
Array
Pot 1
DESCRIPTION
The
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
V
V
W1
V
V
W0
V
V
H1
L0
L1
H0
/R
/R
/R
/R
/R
/R
W0
W1
X9400
L0
H1
L1
H0
All other trademarks mentioned are the property of their respective owners.
bus
July 28, 2006
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Low Noise/Low Power/SPI Bus
interface.
R0 R1
R2 R3
R0 R1
R2 R3
integrates
Register
Counter
Register
(WCR)
Counter
Wiper
(WCR)
Wiper
Each
four
Resistor
potentiometer
digitally
Resistor
Array
Pot 2
Array
Pot 3
X9400
FN8189.3
V
V
V
V
controlled
V
V
L2
H2
L3
H3
W2
W3
/R
/R
/R
/R
/R
/R
L2
H2
L3
H3
W2
W3
has

Related parts for X9400WV24I-2.7T1

X9400WV24I-2.7T1 Summary of contents

Page 1

... L1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9400 Low Noise/Low Power/SPI Bus July 28, 2006 FN8189 ...

Page 2

... X9400YV24I* X9400YV I X9400YV24IZ* X9400YV ZI (Note) X9400YV24Z* X9400YV Z (Note) X9400WS24-2.7* X9400WS F 2.7 to 5.5 X9400WS24I-2.7* X9400WS G X9400WS24IZ-2.7* X9400WS ZG (Note) X9400WV24-2.7* X9400WV F X9400WV24I-2.7* X9400WV G X9400WV24IZ-2.7* X9400WV ZG (Note) X9400WV24Z-2.7* X9400WV ZF (Note) X9400YS24-2.7* X9400YS F X9400YS24I-2.7* X9400YS G X9400YV24-2.7* X9400YV F X9400YV24I-2.7* X9400YV G X9400YV24IZ-2.7* X9400YV ZG (Note) X9400YV24Z-2.7* X9400YV ZF (Note) *Add " ...

Page 3

PIN DESCRIPTIONS Host Interface Pins Serial Output (SO push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial ...

Page 4

PIN NAMES Symbol Description SCK Serial Clock SI, SO Serial Data Device Address Potentiometer Pins (terminal equivalent ...

Page 5

Figure 1. Detailed Potentiometer Block Diagram (One of Four Arrays) Serial Data Path From Interface Circuitry Register 0 Register 2 If WCR = 00[H] then WCR = 3F[H] then V ...

Page 6

Figure 3. Instruction Byte Format Register Select Instructions The four high order bits of the instruction byte specify the operation. The next two bits (R one of the four registers that acted ...

Page 7

Figure 4. Two-Byte Instruction Sequence CS SCK Figure 5. Three-Byte Instruction Sequence (Write) CS SCK Figure 6. Three-Byte Instruction Sequence (Read) CS SCK ...

Page 8

Figure 8. Increment/Decrement Timing Limits SCK INC/DEC CMD Issued Table 1. Instruction Set Instruction I 3 Read Wiper Counter Register 1 Write Wiper Counter Register 1 Read Data Register 1 Write Data Register 1 XFR ...

Page 9

Instruction Format Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (3) “I”: stands for the increment operation, SI held HIGH during active SCK ...

Page 10

Increment/Decrement Wiper Counter Register (WCR) device type device CS identifier addresses Falling A A Edge Global Transfer Data Register (DR) to Wiper Counter Register (WCR) device type device CS identifier addresses Falling ...

Page 11

ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SCK, SCL or any address input with respect to V ......................... -1V to +7V SS Voltage on V+ (referenced ...

Page 12

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter I V supply current (Active) CC1 supply current (Nonvolatile CC2 CC Write current (standby Input leakage current LI I ...

Page 13

A.C. TEST CONDITIONS I nput pulse levels V Input rise and fall times 10ns Input and output timing level V Notes: (4) This parameter is periodically sampled and not 100% tested (5) t and t are the delays required from ...

Page 14

HIGH-VOLTAGE WRITE CYCLE TIMING Symbol t High-voltage write cycle time (store instructions) WR XDCP TIMING Symbol t Wiper response time after the third (last) power supply is stable WRPO t Wiper response time after instruction issued (all load instructions) WRL ...

Page 15

Hold Timing CS SCK HOLD XDCP Timing (for All Load Instructions) CS SCK MSB High Impedance SO XDCP Timing (for Increment/Decrement Instruction) CS SCK ADDR High ...

Page 16

Write Protect and Device Address Pins Timing APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers V R Three terminal Potentiometer; Variable voltage divider Application Circuits Noninverting Amplifier – ...

Page 17

Application Circuits (continued) Attenuator – All -1/2 ≤ G ≤ +1/2 Inverting Amplifier – ...

Page 18

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...

Page 19

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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