ISL90810WIU8 Intersil, ISL90810WIU8 Datasheet - Page 8

• Manufacturer Part Number: ISL90810WIU8
• Description: IC XDCP 256-TAP 10KOHM 8-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90810WIU8

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Typical Performance Curves
Principles of Operation
The ISL90810 is an integrated circuit incorporating one DCP
with its associated registers, and an I
providing direct communication between a host and the
potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of the DCP
contains all zeroes (WR[7:0]: 00h), its wiper terminal (RW) is
closest to its “Low” terminal (RL). When the WR of the DCP
contains all ones (WR[7:0]: FFh), its wiper terminal (RW) is
closest to its “High” terminal (RH). As the value of the WR
increases from all zeroes (0 decimal) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL90810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH.
The WR can be read or written to directly using the I
interface as described in the following sections. The I
interface Address Byte has to be set to 00hex to access the
WR.
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
Wiper Movement Mid Point
From 80h to 7fh
Signal at Wiper (Wiper Unloaded)
8
2
C serial interface
(Continued)
2
C serial
2
C
ISL90810
I
The ISL90810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90810
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90810 the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90810 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power-
up for the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
2
C Serial Interface
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
FIGURE 14. LARGE SIGNAL SETTLING TIME
SCL
2
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
C interface is conducted by
November 10, 2006
FN8234.2